Common-Clock/Single-Clock FIFO - Common-Clock/Single-Clock FIFO - UG573

The common-clock FIFO (also referred to as a single-clock or Synchronous FIFO) is a first-in/first-out queue where the write interface and the read interface share a common clock domain. When using synchronous FIFOs, the CLOCK_DOMAINS attribute should be set to COMMON to eliminate clock cycle latency when asserting or deasserting flags.

The interface of the common-clock FIFO is identical to that of the independent-clocks FIFO, except that either:

• There is only one clock input (CLK), or
• There are two clock inputs (WRCLK and RDCLK) that must be tied to the same clock source (clock buffer)

Because a common-clock FIFO requires no synchronization between clock domains, the internal latencies from a write operation to the deassertion of EMPTY or PROGEMPTY, or from a read operation to the deassertion of FULL or PROGFULL are much faster than in an equivalent independent-clock FIFO.

Also, because a common-clock FIFO does not need to deal with the uncertainty of two unrelated clock domains, it can use the entire memory contents for FIFO storage, rather than reserving a memory location to prevent errors. Because of this, the depth of a common-clock FIFO is one word larger than an equivalent independent-clock FIFO. The following table shows the FIFO capacity in the standard and FWFT modes.