FIFOs can be cascaded in parallel mode based on the block RAM standard/pipelined data out cascade mode utilizing the same multiplexer pins available in the block RAM mode. This cascading mode is available in both FIFO18E2 and FIFO36E2. The parallel mode requires additional user logic and it is the application’s responsibility to provide the appropriate logic for the read and write interfaces for each FIFO in the cascade chain as well as the multiplexer control.
When CASCADE_ORDER = PARALLEL, there are four
additional FIFO inputs available that are used to control the cascade data multiplexers for
that FIFO. These inputs are identical to the equivalent block RAM pins CASOREGIMUX and
CASOREGIMUXEN (for controlling the pipeline register cascade multiplexer), and CASDOMUX and
CASDOMUXEN (for controlling the output cascade multiplexer). In this mode, the special serial
cascade control pins are not available (CASNXTEMPTY, CASPRVEMPTY, CASNXTRDEN,
CASPRVRDEN).
Important: CASCADE_ORDER must
be set to PARALLEL for the cascade input multiplexers to be available.
The following figure shows a parallel cascading example of three FIFOs.
Figure 1. FIFO Parallel Cascade
Important: The CASOREGIMUX and CASOREGIMUXEN
signals are only available in REGISTER_MODE = DO_PIPELINE.