UltraScale™ architecture-based devices have built-in support for cascading FIFOs in series to extend depth without requiring logic resources. Dedicating routing and logic have been added to make this cascading mode available in hardware. Cascading FIFOs in series to expand depth is supported for FIFO18E2 primitives and for FIFO36E2 primitives, and two or more FIFOs can be cascaded up to a full column with some limitations (e.g., a PCIe® block interrupting the column). When cascading FIFOs serially, the first FIFO (the FIFO with the write side interface) must have CASCADE_ORDER = FIRST, the last FIFO (the one with the read interface) must have CASCADE_ORDER = LAST, and all other FIFOs in the chain must have CASCADE_ORDER = MIDDLE. FIFOs with a CASCADE_ORDER of FIRST or MIDDLE must be configured with FIRST_WORD_FALL_THROUGH = TRUE. The LAST FIFO in the chain can be in FWFT or standard mode. The FIFO control logic handles all the handshaking between the blocks and all the read and write interfaces. However, the RDCLK and WRCLK pins for all of the FIFOs in the chain must be connected in a specific way. The WRCLK input of the first FIFO should always use the user’s WRCLK, the RDCLK input of the last FIFO should always use the user’s RDCLK, and all other clock inputs should be connected to the faster of the two clocks. When both the WRCLK and RDCLK of a particular FIFO primitive is connected to the same clock input (same clock buffer source), the FIFO can be configured as a common clock FIFO to reduce the latencies through the FIFOs. The FIFOs can be configured in REGISTERED or UNREGISTERED mode. The REGISTERED mode provides maximum performance at the expense of increased latency for the WRCLK and RDCLK flag deassertion. If resetting the FIFO is required, the RST pins of the FIFOs must be connected by the application (tied to a single reset net). The FIFO control logic does not automatically handle the reset flags RDRSTBUSY and WRRSTBUSY, and therefore the application must monitor those if needed (e.g., ORing them).
The following figure shows a serial cascading example of three FIFOs.
Aside from the dedicated data cascading pins CASDIN, CASDINP, CASDOUT, and CASDOUTP, the FIFO has four additional control pins to support serial cascading. These pins must be connected as follows:
- CASNXTEMPTY output: The CASNXTEMPTY output of a cascaded FIFO with CASCADE_ORDER = FIRST or MIDDLE is the cascaded EMPTY output from the current FIFO to the next in the chain. CASNXTEMPTY connects to the CASPRVEMPTY input on the next FIFO in the chain (configured with CASCADE_ORDER = MIDDLE or LAST), allowing the next FIFO to be aware of when this FIFO is not EMPTY and available for reading.
- CASPRVEMPTY input: The CASPRVEMPTY input of a cascaded FIFO with CASCADE_ORDER = MIDDLE or LAST is the cascaded EMPTY input from the previous FIFO in the chain to the current FIFO. CASPRVEMPTY connects to the CASNXTEMPTY output on the previous FIFO in the chain (configured with CASCADE_ORDER = FIRST or MIDDLE). When CASPRVEMPTY = 0, the current FIFO knows that it can transfer a word of data from the previous FIFO to the current FIFO.
- CASPRVRDEN output: The CASPRVRDEN output of a cascaded FIFO with CASCADE_ORDER = MIDDLE or LAST is the cascaded RDEN output from the current FIFO to the previous FIFO in the chain. CASPRVRDEN connects to the CASNXTRDEN input on the previous FIFO in the chain (configured with CASCADE_ORDER = FIRST or MIDDLE), indicating when to read from the previous FIFO as part of a data word transfer between the two FIFOs.
- CASNXTRDEN input: The CASNXTRDEN input of a cascaded FIFO with CASCADE_ORDER = FIRST or MIDDLE is the cascade RDEN input from the next FIFO to the current FIFO in the chain. CASNXTRDEN connects to the CASPRVRDEN output from the next FIFO in the chain (configured with CASCADE_ORDER = MIDDLE or LAST).