UltraScale architecture-based devices provide the capability to cascade data out from one RAMB36 to the next RAMB36 serially to make a deeper block RAM in a bottom-up fashion. The data out cascading feature is supported for all RAMB36 port widths. The block RAM cascade supports all the features supported by the RAMB36E2 module.
The data flow is always from lower block RAM to upper block RAM. All of the signal routings and the control logic for the cascading feature are implemented in hardware. Multiple block RAMs can be cascaded, as required. All RDCLK inputs of the cascaded set of block RAMs must be driven from the same read clock source. Similarly, all WRCLK inputs of the cascaded set of block RAMs must be driven from the same write clock source. Furthermore, the data cascade capability allows that the lower RAMB18 of the lower RAMB36 can be independently cascaded to the lower RAMB18 of the upper RAMB36. Similarly, the upper RAMB18 of lower RAMB36 can be cascaded to the upper RAMB18 of the upper RAMB36 site.
The following diagram shows a high-level, conceptual view of four cascaded block RAMs.
The block RAM provides flexibility to support many different implementations of the cascade feature. The three multiplexers shown in the previous figure select datapaths and pipeline registers can be dynamically controlled with the input pins.
The following figure shows a more detailed diagram of the functional implementation in a single block RAM block. Three cascade multiplexer selection pins are available when the block RAM is in cascade mode. CASDIMUX selects between either the cascade input data or the direct data input. CASOREGIMUX selects the data output of the block RAM or the cascaded data input to the block RAM's optional output register. This control pin allows pipelined cascading for maximum performance. CASDOMUX selects the data output of the block RAM (with or without the optional register) or the cascaded data input. The latter two cascade multiplexer select pins are registered at the input and have an enable control pin. CASDOUT and CASDIN have dedicated interconnects within a block RAM column. Both the cascade connections and data connection to and from the block RAM are available at the same time.
Although many different use cases can be implemented using the block RAM data cascade feature, this chapter describes three of the most common use cases. The examples shown are based on cascading three block RAM blocks, but more block RAM blocks can be cascaded with some limitations as required by the application in the same fashion.