Byte-Wide Write Enable - Byte-Wide Write Enable - UG573

The byte-wide write enable feature of the block RAM enables the writing of eight-bit (one byte) portions of incoming data. There are four independent byte-wide write enable inputs to the RAMB36E2 true dual-port RAM. In TDP mode for RAMB36E2, there are two ports, A and B, each of which have a 4-bit write enable bus (one bit corresponding to each data byte). In SDP mode for RAMB36E2, there is one write port, which has an 8-bit write enable bus (one bit corresponding to each data byte). The following table summarizes the byte-wide write enables for the 36 Kb and 18 Kb block RAM. Each byte-wide write enable is associated with one byte of input data and one parity bit. The byte-wide write enable inputs must be driven in accordance with the data width configurations. This feature is useful when using block RAM to interface with a microprocessor. Byte-wide write enable is not available in the ECC mode. Byte-wide write enable is further described in Additional RAMB18E2 and RAMB36E2 Primitive Design Considerations. The following figure shows the byte-wide write enable timing diagram for the RAMB36E2.

When the RAMB36E2 is configured for a 36-bit or 18-bit wide datapath, any port can restrict writing to specified byte locations within the data word. If configured in READ_FIRST mode, the DOUT bus shows the previous content of the whole addressed word. In WRITE_FIRST mode, DOUT shows a combination of the newly written enabled byte(s), and the initial memory contents of the unwritten bytes.