The key differences between block RAM and UltraRAM are:
- UltraRAM has one single clock input, is fully synchronous and, unlike the block RAM, does not support independent clock interfaces directly.
- There is no support for configurable port widths of a single 4K x 72 UltraRAM or multiple clock domains. However, the byte write enable feature of the UltraRAM block can be used to support this outside the memory structure itself.
- UltraRAM can only support read or write per port per cycle.
- The simple dual-port (SDP) and true dual-port (TDP) block RAM modes do not directly apply to the UltraRAM. The UltraRAM port behavior can be viewed as a superset of SDP, but not TDP.
- Fixed read behavior; there are no user definable read-first, write-first, no-change modes with UltraRAM.
- Static data cascading; there are no dynamic cascade input or output multiplexer controls with UltraRAM.
- Address collision is not possible with UltraRAM.
- UltraRAM cascades data, address, and control signals, and not only the data lines.
- During the UltraRAM power saving mode (SLEEP), user operations are ignored and content corruption is not possible as long as setup and hold times are met. The memory content is preserved in the sleep power saving mode.
- Automatic power savings can be achieved by using the auto sleep feature that independently controls the wake-up and the sleep mode based on activity. This mode dynamically turns sleep mode on or off for selected UltraRAM blocks in a chain by predicting the activity of many cascaded UltraRAM blocks in a column or across several columns. For single UltraRAM block applications, using this feature would require many cycles of inactivity to be beneficial.
Important: The clock minimum pulse width and
setup/hold time of the UltraRAM address, enable, and sleep pins must not be
violated. Violating the clock minimum pulse width or these setup/hold times
(even if write enable is Low) can corrupt the data contents of the UltraRAM.
This most commonly occurs from an unstable clock or when flip-flops driving
UltraRAM control pins are asynchronously reset, such as a system wide reset.
To avoid this issue, ensure stable clocks and design with synchronous resets
for both assertion and deassertion. When the clock is not stable, disable
the clock buffer or disable logic driving the UltraRAM control pins or
deassert the UltraRAM EN input.