Block RAM and FIFO ECC Port Descriptions - Block RAM and FIFO ECC Port Descriptions - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID: UG573
Release Date: 2025-11-18
Revision: 1.14 English

The following table lists and describes the block RAM and FIFO ECC-related I/O port names.

Table 1. RAMB36E2 and FIFO32E2 ECC Port Names and Descriptions
Port Name	Signal Description
INJECTSBERR	Injects a single-bit error if ECC is used. Creates a single-bit error at a particular block RAM bit location when asserted during write. The block RAM ECC logic corrects this error when this location is read back. The error is created in bit DIN[30].
INJECTDBERR	Injects a double-bit error if ECC is used. Creates a double-bit error at two particular block RAM bit locations when asserted during write. The block RAM ECC logic flags a double-bit error when this location is read back. When both INJECTSBERR and INJECTDBERR signals are simultaneously asserted, a double-bit error is injected. The errors are created in bits DIN[30] and DIN[62].
ECCPARITY[7:0]	ECC encoder output bus for ECC used in encode-only mode. This output cannot be cascaded.
SBERR	ECC single-bit error output status. See also the dedicated cascade pins in this table when using the block RAM and FIFO in ECC cascade mode.¹
DBERR	ECC double-bit error output status. See also the dedicated cascade pins in this table when using the block RAM and FIFO in ECC cascade mode.¹
RDADDRECC[8:0]	ECC read address. Address pointer to the data currently read out. The data and corresponding address are available in the same cycle. This output is not supported in the FIFO and cannot be cascaded.
CASINSBITERR	ECC single-bit error input in cascade mode. Cascade SBERR error bit status from the previous block RAM/FIFO.
CASOUTSBITERR	ECC single-bit error output in cascade mode. Cascade SBERR error bit status to the next block RAM/FIFO.
CASINDBITERR	ECC double-bit error input in cascade mode. Cascade DBERR error bit status from the previous block RAM/FIFO.
CASOUTDBITERR	ECC double-bit error output in cascade mode. Cascade DBERR error bit status to the next block RAM/FIFO.
ECCPIPECE	ECC pipeline register clock enable when EN_ECC_PIPE = TRUE. This is available only in ECC mode when EN_ECC_READ = TRUE. In the FIFO, this function is controlled by the FIFO logic and not available to the application.
Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error detected and corrected on DOUT (but not corrected in the memory), and double-bit error detected without correction. SBITERR and DBITERR indicate these three conditions.