Block RAM Library Primitives - Block RAM Library Primitives

The block RAM library primitives, RAMB18E2 and RAMB36E2, are the basic building blocks for all block RAM configurations. Other block RAM primitives and macros are based on these primitives. Some block RAM attributes can only be configured using one of these primitives (for example, pipeline register, cascade).

The input and output data buses are represented by two buses for 9-bit width (8 + 1), 18-bit width (16 + 2), and 36-bit width (32 + 4) configurations. The ninth bit associated with each byte can store parity/error correction bits or serve as additional data bits. No specific function is performed on the ninth bit. The separate bus for parity bits facilitates some designs. However, other designs safely use a 9-bit, 18-bit, or 36-bit bus by merging the regular data bus with the parity bus. Read/write and storage operations are identical for all bits, including the parity bits.

The following figure illustrates all the I/O ports of the 36 Kb true dual-port block RAM primitive (RAMB36). The following table lists these primitives.

Note: ECC pins are not shown in the following figure. For more information, see Built-in Error Correction.

Figure 1. Block RAM Port Signals (RAMB36E2)

Table 1. Block RAM and FIFO Primitives
Primitive	Description
RAMB36E2	When used as TDP memory, RAMB36E2 supports port widths of x1, x2, x4, x9, x18, and x36. When used as SDP memory, the read or write port width is x64 or x72. Alternate port widths are x1, x2, x4, x9, x18, x36, and x72. In ECC mode, RAMB36E2 supports 64-bit ECC encoding and decoding.
RAMB18E2	When used as TDP memory, RAMB18E2 supports port widths of x1, x2, x4, x9, and x18. When used as SDP memory, the read or write port width is x32 or x36. Alternate port widths are x1, x2, x4, x9, x18, and x36.
FIFO36E2	FIFO36E2 supports port widths of x4, x9, x18, x36, and x72 for either port. When the port width is x72, ECC is optionally supported.
FIFO18E2	The FIFO18E2 supports port widths of x4, x9, x18, and x36 for either port.

The following table shows the port names and descriptions of the primitives outlined in the preceding table. The ECC ports are described in Built-in Error Correction.

Table 2. RAMB36E2 and RAMB18E2 Port Names and Descriptions
Port Name	Description
DINADIN[31:0]	Port A data inputs addressed by ADDRARDADDR. See Table 5 for SDP usage port name mapping.
DINPADINP[3:0]	Port A data parity inputs addressed by ADDRARDA.DDR. See Table 5 for SDP usage port name mapping.
DINBDIN[31:0]	Port B data inputs addressed by ADDRBWRADDR. See Table 5 for SDP usage port name mapping.
DINPBDINP[3:0]	Port A data parity inputs addressed by ADDRBWRADDR. See Table 5 for SDP usage port name mapping.
ADDRARDADDR [14:0]	Port A address input bus. When used as SDP memory, this is the RDADDR bus.
ADDRBWRADDR[14:0]	Port B address input bus. When used as SDP memory, this is the WRADDR bus.
ADDRENA	ADDRENA enables or disables the capture of a new address on port A. When disabled (Low) the old, latched address is used.
ADDRENB	ADDRENB enables or disables the capture of a new address on port B. When disabled (Low) the old, latched address is used.
WEA[3:0]	Port A byte-wide write enable. When used as SDP memory, this port is not used.
WEBWE[7:0]	Port B byte-wide write enable. In SDP mode, this is the byte-wide write enable.
ENARDEN	Port A enable. When used as SDP memory, this is RDEN.
ENBWREN	Port B enable. When used as SDP memory, this is WREN.
RSTREGARSTREG	Synchronous output register set/reset as initialized by SRVAL_A (DOA_REG = 1). RSTREG_PRIORITY_A determines the priority over REGCE. When used as SDP memory, this is RSTREG.
RSTREGB	Synchronous output register set/reset as initialized by SRVAL_B (DOA_REG = 1). RSTREG_PRIORITY_B determines the priority over REGCE.
RSTRAMARSTRAM	Synchronous output latch set/reset as initialized by SRVAL_A (DOB_REG = 0). When used as SDP memory, this is RSTRAM.
RSTRAMB	Synchronous output latch set/reset as initialized by SRVAL_B (DOB_REG = 0).
CLKARDCLK	Port A clock input. When used as SDP memory, this is RDCLK.
CLKBWRCLK	Port B clock input. When used as SDP memory, this is WRCLK.
REGCEAREGCE	Port A output register clock enable (DOA_REG = 1). When used as SDP memory, this is REGCE.
REGCEB	Port B output register clock enable (DOB_REG = 1).
CASDINA[31:0]	Port A cascade data input connected to data output of lower block RAM. For RAMB18E2: CASDINA[15:0].
CASDINPA[3:0]	Port A cascade parity data input connected to parity data output of lower block RAM. For RAMB18E2: CASDINPA[1:0].
CASDINB[31:0]	Port B cascade data input connected to data output of lower block RAM. For RAMB18E2: CASDINB[15:0].
CASDINPB[3:0]	Port B cascade parity data input connected to parity data output of lower block RAM. For RAMB18E2: CASDINPB[1:0].
CASDOUTA[31:0]	Port A cascade data output connected to CASDINA[31:0] of upper block RAM. For RAMB18E2: CASDOUTA[15:0].
CASDOUTPA[3:0]	Port A cascade parity data output connected to CASDINPA[3:0] of upper block RAM. For RAMB18E2: CASDOUTPA[1:0].
CASDOUTB[31:0]	Port B cascade data output connected to CASDINB[31:0] of upper block RAM. For RAMB18E2: CASDOUTB[15:0].
CASDOUTPB[3:0]	Port B cascade parity data output connected to CASDINPB[3:0] of upper block RAM. For RAMB18E2: CASDOUTPB[1:0].
CASDOMUXA	Selects input to control the data cascade output multiplexer for port A.
CASDOMUXEN_A	Enables control for the CASDOMUXA register.
CASDOMUXB	Selects input to control the data cascade output multiplexer for port B.
CASDOMUXEN_B	Enables control for the CASDOMUXB register. When used as SDP memory, this port is not used.
CASOREGIMUXA	Selects input to control the cascade multiplexer before the output register for Port A.
CASOREGIMUXEN_A	Enables control for the CASOREGIMUXA register.
CASOREGIMUXB	Selects input to control the cascade multiplexer before the output register for Port B. When used as SDP memory, this port is not used.
CASOREGIMUXEN_B	Enables control for the CASOREGIMUXB register. When used as SDP memory, this port is not used.
CASDIMUXA	Selects input to control the cascade DIN multiplexer for Port A.
CASDIMUXB	Selects input to control the cascade DIN multiplexer for Port B. When used as SDP memory, this port is not used.
DOUTADOUT[31:0]	Port A data output bus addressed by ADDRARDADDR. See Table 5 for SDP usage port name mapping. RAMB18E2: DOUTADOUT[15:0].
DOUTPADOUTP[3:0]	Port A parity output bus addressed by ADDRARDADDR. See Table 5 for SDP usage port name mapping. RAMB18E2: DOUTPADOUTP[1:0].
DOUTBDOUT[31:0]	Port B data output bus addressed by ADDRBWRADDR. See Table 5 for SDP usage port name mapping. RAMB18E2: DOUTBDOUT[15:0].
DOUTPBDOUTP[3:0]	Port B parity output bus addressed by ADDRBWRADDR. See Table 5 for SDP usage port name mapping. RAMB18E2: DOUTPBDOUTP[1:0].
SLEEP	Dynamic power gating.

Block RAM Library Primitives - Block RAM Library Primitives - UG573

UltraScale Architecture Memory Resources User Guide (UG573)