In addition to distributed RAM and high-speed SelectIO™ memory interfaces, UltraScale architecture-based devices feature a large number of 36 Kb block RAMs. Each 36 Kb block RAM contains two independently controlled 18 Kb RAMs. Block RAMs are placed in columns within the clock regions (CRs) and across the device. The block RAM data output blocks are cascadable to enable a deeper memory implementation, have a sleep mode for power savings, and have selectable write mode operations.