Block RAM Initialization in VHDL or Verilog Code - Block RAM Initialization in VHDL or Verilog Code

Block RAM Initialization in VHDL or Verilog Code - Block RAM Initialization in VHDL or Verilog Code - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID

UG573

Release Date

2025-11-18

Revision

1.14 English

Block RAM attributes and content can be initialized in VHDL or Verilog code for both synthesis and simulation by using generic maps (VHDL) or defparams (Verilog) within the instantiated component. Modifying the values of the generic map or defparam affects both the simulation behavior and the implemented synthesis results. Inferred block RAM can be initialized as well. The AMD Vivado™ Design Suite templates include the code to instantiate the RAMB primitives.