Block RAM ECC VHDL and Verilog Templates - Block RAM ECC VHDL and Verilog Templates

Block RAM ECC VHDL and Verilog Templates - Block RAM ECC VHDL and Verilog Templates - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID

UG573

Release Date

2025-11-18

Revision

1.14 English

VHDL and Verilog primitive instantiation templates and Xilinx parameterized macros (XPMs) for block RAM with ECC are available in the Vivado Design Suite.