Block RAM Attributes - Block RAM Attributes

Block RAM Attributes - Block RAM Attributes - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID

UG573

Release Date

2025-11-18

Revision

1.14 English

The following table lists the RAMB18E2 and RAMB36E2 attributes. All attribute code examples are discussed in Block RAM Initialization in VHDL or Verilog Code. Further information on using these attributes is available in Additional RAMB18E2 and RAMB36E2 Primitive Design Considerations.

Table 1. RAMB18E2 and RAMB36E2 Attributes
Attributes	Values	Default	Type	Description
CASCADE_ORDER_A	FIRST, MIDDLE, LAST, NONE	NONE	String	Specifies the order of the cascaded block RAMs from the bottom to the top of the chain for port A.
CASCADE_ORDER_B	FIRST, MIDDLE, LAST, NONE	NONE	String	Specifies the order of the cascaded block RAMs from the bottom to the top of the chain for port B.
CLOCK_DOMAINS	INDEPENDENT, COMMON	INDEPENDENT	String	Either independent clocks connected to port A and B or a single, common clock connected to port A and B.
DOA_REG	0, 1	1	Decimal	A value of 1 enables the optional output registers of the RAM port A. Applies to all port A outputs in both TDP and SDP memory usage.
DOB_REG	0, 1	1	Decimal	A value of 1 enables the optional output registers of the RAM port B. Applies to all port B outputs in both TDP and SDP memory usage.
ENADDRENA	FALSE, TRUE	FALSE	String	Specifies if the address enable pin on port A is enabled.
ENADDRENB	FALSE, TRUE	FALSE	String	Specifies if the address enable pin on port B is enabled.
INIT_A	RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value	RAMB18E2: `18'h00000000` RAMB36E2: `36'h0000000000000000`	Hex	Specifies the initial value of the port A outputs after configuration. Applies to all port A outputs in both TDP and SDP memory usage.
INIT_B	RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value	RAMB18E2: `18'h00000000` RAMB36E2: `36'h0000000000000000`	Hex	Specifies the initial value of the port B outputs after configuration. Applies to all port B outputs in both TDP and SDP memory usage.
RAMB18E2: INIT_00 to INIT_3F RAMB36E2: INIT_00 to INIT_7F	A 256-bit hex value	All 0	Hex	Initializes the data content of the block RAM.
RAMB18E2: INITP_00 to INITP_07 RAMB36E2: INITP_00 to INITP_0F	A 256-bit hex value	All 0	Hex	Initializes the parity content of the block RAM.
RDADDRCHANGEA¹	FALSE, TRUE	FALSE	String	Specifies if the port A read address compare feature is turned on.
RDADDRCHANGEB¹	FALSE, TRUE	FALSE	String	Specifies if the port B read address compare feature is turned on.
READ_WIDTH_A	RAMB18E2: 0, 1, 2, 4, 9, 18, 36 (SDP usage) RAMB36E2: 0, 1, 2, 4, 9, 18, 36, 72 (SDP usage)	0	Decimal	Specifies the data width for read port A, including parity bits. This value must be 0 if port A is not used.
READ_WIDTH_B	RAMB18E2: 0, 1, 2, 4, 9, 18 RAMB36E2: 0, 1, 2, 4, 9, 18, 36	0	Decimal	Specifies the data width for read port B including parity bits. This value must be 0 if port B is not used. Not used for SDP memory usage.
RSTREG_PRIORITY_A	RSTREG, REGCE	RSTREG	String	Selects the priority of RESET or CE for the optional output registers. Applies to all port A outputs in both TDP and SDP memory usage.
RSTREG_PRIORITY_B	RSTREG, REGCE	RSTREG	String	Selects the priority of RESET or CE for the optional output registers. Applies to all port B outputs in both TDP and SDP memory usage.
SLEEP_ASYNC	FALSE, TRUE	FALSE	String	Determines if the SLEEP pin is synchronous or asynchronous to the clock.
SRVAL_A	RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value	RAMB18E2: `18'h00000000` RAMB36E2: `36'h0000000000000000`	Hex	Specifies the initialization value of the output latches or register when the synchronous reset (RSTREG) is asserted. Applies to all port A outputs in both TDP and SDP memory usage.
SRVAL_B	RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value	RAMB18E2: `18'h00000000` RAMB36E2: `36'h0000000000000000`	Hex	Specifies the initialization value of the output latches or register when the synchronous reset (RSTREG) is asserted. Applies to all port B outputs in both TDP and SDP memory usage.
WRITE_MODE_A²	WRITE_FIRST, NO_CHANGE, READ_FIRST	WRITE_FIRST	String	Specifies output behavior of write port A. See Write Modes.
WRITE_MODE_B²	WRITE_FIRST, NO_CHANGE, READ_FIRST	WRITE_FIRST	String	Specifies output behavior of write port B. See Write Modes.
WRITE_WIDTH_A	RAMB18E2: 0, 1, 2, 4, 9, 18 RAMB36E2: 0, 1, 2, 4, 9, 18, 36	0	Decimal	Specifies the data width for write port A, including parity bits. This value must be 0 if the port is not used. When used as SDP memory, this attribute is not valid.
WRITE_WIDTH_B	RAMB18E2: 0, 1, 2, 4, 9, 18, 36 (SDP usage) RAMB36E2: 0, 1, 2, 4, 9, 18, 36, 72 (SDP usage)	0	Decimal	Specifies the data width for write Port B, including parity bits. This value must be 0 if port B is not used.
In the UltraScale family (not UltraScale+), this feature is only supported for uninitialized block RAM content and registers (initialized to the default of zero). In SDP mode, the WRITE_MODE_A and WRITE_MODE_B must have the same value.