Each port accesses the same set of 18,432 or 36,864 memory cells using an addressing scheme dependent on whether it is a RAMB18E2 or RAMB36E2. The physical RAM locations addressed for a particular width are determined using these formulae (of interest only when the two ports use different aspect ratios):
END = ((ADDR + 1) × Width) –1
START = ADDR × Width
The following table shows low-order address mapping for each port width.
| Port Width | Parity Locations | Data Locations | ||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | N.A. | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
| 2 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||||||||||||||||
| 4 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||
| 8 + 1 | 3 | 2 | 1 | 0 | 3 | 2 | 1 | 0 | ||||||||||||||||||||||||||||
| 16 + 2 | 1 | 0 | 1 | 0 | ||||||||||||||||||||||||||||||||
| 32 + 4 | 0 | 0 | ||||||||||||||||||||||||||||||||||