To determine when the UltraRAM can activate sleep and wake-up in the auto sleep mode, look-ahead information is required. The byte write enable, read/write, data, and lower address inputs must be delayed with respect to the enable and higher address inputs. These inputs are delayed by pipeline stages equal to the AUTO_SLEEP_LATENCY setting, which can be between 3 and 15. FIFOs or linear shift registers can be used to accomplish this in the FPGA fabric. Other signals, such as INJECT and CE inputs, must also be pipeline aligned if used. See Auto Sleep Latency – AUTO_SLEEP_LATENCY for more information.
EN_INT_DLY is delayed by AUTO_SLEEP_LATENCY from input EN to show the pipeline alignment with other inputs. DOUT holds previous read data during sleep cycles when OREG_ECC=TRUE.
After EN_INT_DLY is deasserted, an extra idle cycle is inserted before the sleep cycle because of the OREG stage. If the OREG pipeline is set to TRUE, an extra cycle is needed to ensure the read data has propagated to the output before the UltraRAM enters sleep. Consequently, there is a wait of two cycles after EN_INT_DLY deasserts before starting the sleep cycles. Additionally, the sleep cycle is also a function of AUTO_SLEEP_LATENCY, which dictates the number of idle cycles needed to go to sleep (the delay from EN to EN_INT_DLY).
Auto sleep wake-up always occurs one cycle before EN_INT_DLY goes High to guarantee sufficient wakeup time before a next read or write cycle. Wake-up is only a function of EN_INT_DLY_A/B (and EN by extension) rising and no other inputs.
EN_INT_DLY is delayed by AUTO_SLEEP_LATENCY from input EN to show the pipeline alignment with other inputs. DOUT holds previous read data during sleep cycles when OREG_ECC=TRUE.
The AUTO_SLEEP_LATENCY dictates the number of idle cycles needed for the UltraRAM to go to sleep. In the previous figure, it is set to eight, which means at least eight cycles are needed between EN_INT_DLY deasserting and the next assertion of EN_INT_DLY to see any sleep cycles. In the later cycles (after sleep/wake-up), there is not enough idle time and the UltraRAM does not go to sleep again.
See the attribute description in Auto Sleep Latency – AUTO_SLEEP_LATENCY for the number of expected sleep cycles.
EN_INT_DLY is delayed by AUTO_SLEEP_LATENCY from input EN to show the pipeline alignment with other inputs. DOUT holds previous read data when there are no sleep cycles, but is driven to “0” during sleep cycles when OREG_ECC=FALSE.
EN_INT_DLY is delayed by AUTO_SLEEP_LATENCY from input EN to show the pipeline alignment with other inputs. DOUT holds the previous read data when there are no sleep cycles, but is driven to “0” during sleep cycles when OREG_ECC=FALSE.