Address Collision - Address Collision - UG573

An address collision is when both block RAM ports access the same address location in the same clock cycle. There are two fundamental clock type setups, common clock and independent clock. Common (synchronous) clocks are driven by a common clock buffer driver. All other CLKA and CLKB connections are considered independent (asynchronous) clocks. The CLOCK_DOMAINS attribute must also be set appropriately. See Table 1 for legal and default values. If no address collisions are expected or possible (SDP configurations) to save power, the recommended write mode is NO_CHANGE. Using READ_FIRST mode has a 15% power penalty over NO_CHANGE and should only be used when necessary for functionality or address collision mitigation.

• When both ports are reading, the operations complete successfully.
• When both ports are writing different data, the memory location is written with non-deterministic data.
• When one port is writing and the other port is reading, the write is always successful but the resulting read memory value can vary. See the following tables.

In the following tables:

• WE = Write enable is active-High, 1 = Write, 0 = Read; applies at the byte-level when using the byte-wide write-enable feature
• RF = READ_FIRST, WF = WRITE_FIRST, NC = NO_CHANGE
• X = Undeterministic value
• DIA = Port A data input, DIB = Port B data input
• Resulting data out applies to DOUT, DOUTP, SBITERR, and DBITERR