Address Bit Decoding - Address Bit Decoding - UG573

• Row 1 Multicast

  ADDR15:12 = 0011 multicast to columns 1+2

  ADDR15:12 = 0101 multicast to columns 1+3

  ADDR15:12 = 0110 multicast to columns 2+3

  ADDR15:12 = 0111 multicast to columns 1+2+3

  ADDR15:12 = 1101 multicast to columns 1+2+4

  etc.

  ADDR15:12 = 1111 multicast to columns 1+2+3+4

• Row/Column Addr

  ADDR19:16 = 0001 – 0011 rows 2,3,4, column 1

  ADDR19:16 = 0101 – 0111 rows 2,3,4, column 2

  ADDR19:16 = 1001 – 1011 rows 2,3,4, column 3

  ADDR19:16 = 1101 – 1111 rows 2,3,4, column 4

The UltraScale+ device is supported by the Vivado Design Suite, which includes several code templates to help target the available silicon resources. There are three methods of RTL design entry to use the UltraRAM memories:

• Use the Xilinx Parameterized Macros (XPM) starting with the 2016.1 Vivado tools release.
• Infer an RTL memory without ECC and use the ram_style attribute set to “ultra.”
• Instantiate the device primitive.

Examples for these methods are in the Vivado language templates accessible from the main Vivado tools menu by selecting Tools > Language Templates.