Revision History - Revision History

Section	Revision Summary
05/29/2025 Version 1.11
General updates	Added support for Spartan UltraScale+ devices.
Clocking Architecture Overview	Updated number of I/Os per bank in first bullet.
Key Differences from 7 Series FPGAs	Updated bullet on MMCM output clock frequencies.
Key Differences of Spartan UltraScale+ FPGAs from Other UltraScale+ FPGAs	Added new section.
Global Clock Inputs	Updated description of BUFGCE output in first paragraph. Updated description of I/O pins and banks in second paragraph.
Clock Structure	Updated description of routing tracks in first paragraph. Added Table 1. Added note after Figure 3.
Overview	Added description of CMT in Spartan UltraScale+ devices, including Figure 1.
Dynamic Phase Shift Interface in the MMCM	Updated description of phase shift in second paragraph.
Figure 1	Updated arrows to counter output O1 to originate from 180° phase waveform.
Table 1	Updated 1.
MMCM Application Example	Updated to CLKOUT0_DIVIDE_F.
PLLs	Added sentence about Spartan UltraScale+ devices.
PLL Primitives	Added paragraph about PLL primitives in Spartan UltraScale+ devices. Added Figure 2.
PLLE3_BASE, PLLE4_BASE, and PLL4XP_BASE Primitive	Added PLL4XP_BASE Added Table 2.
PLLE4XP_ADV Primitive	Added section.
Table 1	Changed CLKOUTPHY to CLKOUTPHY_N, CLKOUTPHY_P. Added PLLE4XP ports.
CLKFBOUT – Dedicated PLL Feedback Output	Add note about Spartan UltraScale+ devices.
Additional PLLE4XP Port Descriptions	Added section.
Table 2	Added table.
MMCM Registers	Added cps1704713398896.html#cps1704713398896__table_N1174B_N1001A_N10018_N10001.
PLL Registers	Added kto1704713399115.html#kto1704713399115__table_svn_yhr_zzb.
02/01/2023 Version 1.10.2
General updates	Editorial updates only. No technical content updates.
08/25/2021 Version 1.10.1
General updates	Editorial updates only. No technical content updates.
08/28/2020 Version 1.10
Clock Management Tile	Updated Figure 1. Updated the table for register 15 in MMCM Registers.
10/31/2019 Version 1.9
Clocking Resources	Updated UltraScale+ note in BUFG_GT and BUFG_GT_SYNC.
Clock Management Tile	Updated Table 1 footnote. Updated Spread-Spectrum Clock Generation section with new content and equations. Updated Table 1.
12/19/2018 Version 1.8
Clock Management Tile	Updated the example in Determine the Input Frequency section. Added the new sections Dynamic Reconfiguration Port and Clocking Guidelines.
04/09/2018 Version 1.7
Clocking Resources	Updated the BUFG_GT and BUFG_GT_SYNC section.
Clock Management Tile	In Table 1, updated note 3.
06/06/2017 Version 1.6
Clock Management Tile	In Table 1, updated the description of BUF_IN for the COMPENSATION attribute.
03/15/2017 Version 1.5
Clocking Resources	Updated the discussion on page 14. Added clarification to the BUFG_GT and BUFG_GT_SYNC section.
Clock Management Tile	Updated the Dynamic Phase Shift Interface in the MMCM section. Added Table 2 and Table 4. In Table 1, updated the descriptions for CLKOUT[0:1]_PHASE and CLKFBOUT_PHASE.
12/12/2016 Version 1.4
Overview	Updated the discussion in Key Differences from 7 Series FPGAs about the differences between clock capable and global clock pins.
Clocking Resources	Added clarification to the Global Clock Inputs section. Added further information following Figure 3. Updated the BUFGCE_DIV section. Revised the BUFG_GT_SYNC description after Figure 1 to include the UltraScale+ devices.
Clock Management Tile	Added the UltraScale+ device MMCME4 and PLLE4 primitives to the MMCM Primitives and PLL Primitives sections. Updated the description of PSCLK cycles in the Dynamic Phase Shift Interface in the MMCM section. Added a Recommended note to CLKOUT[0:6] – Output Clocks. Updated the CLKINSTOPPED – Input Clock Status section. Added CLKFBOUT and CLKFBIN to Table 1 and their descriptions below the table. Updated the CLKOUTPHYEN – PHY Clock Enable description. Added Figure 1 and Figure 2. In Table 1, updated the DIVCLK_DIVIDE allowed values and added PHY_ALIGN to the COMPENSATION attribute.
General updates	Updated the Please Read: Important Legal Notices section.
11/24/2015 Version 1.3
Overview	Under Introduction to the UltraScale Architecture, added new introductory text for UltraScale+ devices. Added ninth bullet under Key Differences from 7 Series FPGAs.
Clocking Resources	Updated first paragraph under Global Clock Inputs to include information about HDGC pins. Updated first paragraph under Clock Structure. Added Important note under Clock Buffers. Added second paragraph under BUFCE_LEAF Clock Buffer. Added first two sentences under BUFG_GT and BUFG_GT_SYNC. Added BUFG_PS section.
Clock Management Tile	Updated Frequency Synthesis Using Fractional Divide in the MMCM by changing 0.125 degrees to 0.125. Revised the heading Static Phase Shift Mode (MMCM and PLL) by adding (MMCM and PLL). Revised the heading MMCM Clock Divide Dynamic Change by adding MMCM. Added Important note under CLKFBIN – Feedback Clock Input. In Table 1, added a row of UltraScale+ device MMCM attributes for CLKFBOUT_MULT_F, changed default value for COMPENSATION from ZHOLD to AUTO, revised the COMPENSATION description, and added note 4 and note 5. In Table 1, added a row of UltraScale+ device PLL attributes for CLKFBOUT_MULT, revised the COMPENSATION description, and added note 1. Added Dynamic Reconfiguration Port section.
References	Updated section.
02/23/2015 Version 1.2
Clock Management Tile	In Table 1, changed the Allowed Values attribute for CLKIN1_PERIOD and CLKIN2_PERIOD. In Table 1, changed the Allowed Values attribute for CLKIN_PERIOD.
08/21/2014 Version 1.1
Clocking Resources	Replaced clock-capable with global clock in Global Clock Inputs. Updated Byte Clock Inputs. Added BUFG_GT_SYNC to BUFG_GT and BUFG_GT_SYNC.
Clock Management Tile	Updated Figure 1 and added tip for Table 1. Updated Figure 1.
12/10/2013 Version 1.0
Initial release.	N/A

Revision History - Revision History - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)