There are two PLLs per CMT that provide clocking to the PHY logic and I/Os. In addition, they can be used as frequency synthesizers for a wide range of frequencies, serve as jitter filters, and provide basic phase shift capabilities and duty cycle programming. The PLLs differ from the MMCM in number of outputs, cannot deskew clock nets, and do not have advanced phase shift capabilities, Multipliers and input dividers have a smaller value range and do not have many of the other advanced features of the MMCM. In Spartan UltraScale+ devices with XP5IO, apart from two PLLs per CMT, there are two PLLXP2 per CMTXP (that are adjacent to the XP5IO banks).