PLLE4XP_ADV Primitive - PLLE4XP_ADV Primitive - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2025-05-29
Revision
1.11 English
Table 1. PLLE4XP_ADV Ports
Description Ports
Clock input CLKIN, DCLK, CLKFBIN
Control and data input RST, RST_DMC,CLKOUTPHYEN, CLKOUTPHY_DMCEN, DWE, DEN, DADDR, DI
Clock output CLKOUT0, CLKOUT1, CLKOUT0B, CLKOUT1B, CLKOUTPHY, CLKFBOUT
Status and data output LOCKED, LOCKED_DMC,DO, DRDY
Power control PWRDWN