The PLLE#_BASE and PLL4XP_BASE primitive
provides access to the most frequently used features of a stand-alone PLL. Clock deskew,
frequency synthesis, and duty cycle programming are available to use with the PLLE#_BASE.
The ports are listed in the following table.
Table 1. PLLE#_BASE Ports
| Description |
Ports |
| Clock input |
CLKIN, CLKFBIN |
| Control inputs |
RST, CLKOUTPHYEN |
| Clock output |
CLKOUT0, CLKOUT1, CLKOUT0B,
CLKOUT1B, CLKOUTPHY, CLKFBOUT |
| Status and data
outputs |
LOCKED |
| Power control |
PWRDWN |
Table 2. PLLE4XP_BASE Ports
| Description |
Ports |
| Clock input |
CLKIN, CLKFBIN |
| Control inputs |
RST, RST_DMC, CLKOUTPHYEN, CLKOUTPHY_DMCEN |
| Clock output |
CLKOUT0, CLKOUT1, CLKOUT0B, CLKOUT1B, CLKOUTPHY,
CLKFBOUT |
| Status and data outputs |
LOCKED, LOCKED_DMC |
| Power control |
PWRDWN |