The PLLE#_ADV primitive provides access to all PLLE#_BASE features plus additional ports for access to the DRP. The ports are listed in the following table.
| Description | Ports |
|---|---|
| Clock input | CLKIN, DCLK, CLKFBIN |
| Control and data input | RST, CLKOUTPHYEN, DWE, DEN, DADDR, DI |
| Clock output | CLKOUT0, CLKOUT1, CLKOUT0B, CLKOUT1B, CLKOUTPHY, CLKFBOUT |
| Status and data output | LOCKED, DO, DRDY |
| Power control | PWRDWN |