PLL Registers - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)
Document ID
UG572
Release Date
2025-05-29
Revision
1.11 English

The PLL DRP register set is similar and runs parallel with that of the MMCM. The number of possible changeable registers in the PLL DRP resister set is smaller than that of the MMCM because the PLL has only two clock outputs and does not use a selectable VCO output multiplexer and interpolator.

Reg 73 ADDR: 0x73
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0   1                        
Access R/W R/W   R/W                        
15 mc_gts_wait Wait for the GTS_CFG_B signal before starting the LOCKED process.
14 mc_startup_wait Wait during the configuration start-up cycle for the MMCM to lock.
12 mc_mmcm_en Enable the PLL.
Reg 4F ADDR: 0x4F
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0     0 0     0 0     0        
Access R/W     R/W R/W     R/W R/W     R/W        
15 mc_res(3) Loop filter resistor setting.
12 mc_res(2)
11 mc_res(1)
8 mc_res(0) Loop filter high frequency capacitor setting.
7 mc_lfhf(1)
4 mc_lfhf(0)
Reg 4E ADDR: 0x4E
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0     0 0     0 0     0 1      
Access R/W     R/W R/W     R/W R/W     R/W R/W      
15 mc_cp(3) Charge pump settings.
12 mc_cp(2)
11 mc_cp(1)
8 mc_cp(0)
7 mc_cp_bias_trip_set Control of the low trip point sense circuit.
4 mc_cp_res(1) Charge pump reference current control.
3 mc_cp_res(0)
Reg 1A ADDR: 0x1A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default   0 0 0 1 1 1 1 1 1 1 0 1 0 0 1
Access   R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
14:10 mc_lock_ref_dly[4:0] Window setting for the lock circuit of the reference clock.
9:0 mc_lock_sat_high[9:0] Maximum value of the lock counter. Default value is d1001 .
Reg 19 ADDR: 0x19
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default   0 0 0 1 1 0 0 0 0 0 0 0 0 0 1
Access   R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
14:10 mc_lock_fb_dly[4:0] Window setting for the lock circuit on the feedback clock.
9:0 mc_unlock_cnt[9:0] Counter setting the number of clock cycles the PLL needs to have CLKREF and CLKFB misaligned within a certain window before deasserting the LOCKED output. Default value is 1.
Reg 18 ADDR: 0x18
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default             0 0 0 0 0 0 0 0 0 1
Access             R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
9:0 mc_lock_cnt[9:0] Counter setting the number of clock cycles the PLL needs to have CLKREF and CLKFB aligned within a certain window before the LOCKED output is asserted. Default value is 1000 .
Reg 16 ADDR: 0x16
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default     0 1 0 0 0 0 0 1 0 0 0 0 0 1
Access     R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
13 mc_divck_edge High to low clock edge transition control.
12 mc_divck_nocount Bypass counter.
11:6 mc_divck_ht[5:0] Counter high time.
5:0 mc_divck_lt[5:0] Counter low time.
Reg 15 ADDR: 0x15
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default                 0 1 0 0 0 0 0 0
Access                 R/W R/W R/W R/W R/W R/W R/W R/W
7 mc_ckfbout_edge High to low clock edge transition control.
6 mc_ckfbout_nocount Bypass counter.
5:0 mc_ckfbout_dt[5:0] Counter delay.
Reg 14 ADDR: 0x14
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default     0 1 0 0 0 0 0 1 0 0 0 0 0 1
Access     R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
12 mc_ckfbout_en Counter enable.
11:6 mc_ckfbout_ht[5:0] Counter high time.
5:0 mc_ckfbout_lt[5:0] Counter low time.
Reg 0B ADDR: 0x0B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default   0 0           0 1 0 0 0 0 0 0
Access   R/W R/W           R/W R/W R/W R/W R/W R/W R/W R/W
14:13 mc_ckoutphy_mode[1:0] CLKOUTPHY mode (VCO_2X, VCO, VCO_HALF).
7 mc_ckout1_edge High to low clock edge control.
6 mc_ckout1_nocount Counter bypass.
5:0 mc_ckout1_dt[5:0] Counter delay.
Reg 0A ADDR: 0x0A
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default       1 0 0 0 0 0 1 0 0 0 0 0 0
Access       R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
12 mc_ckout1_en Counter enable.
11:6 mc_ckout1_ht[5:0] Counter high time.
5:0 mc_ckout1_lt[5:0] Counter low time.
Reg 09 ADDR: 0x09
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default                 0 1 0 0 0 0 0 0
Access                 R/W R/W R/W R/W R/W R/W R/W R/W
7 mc_ckout0_edge High to low clock edge control.
6 mc_ckout0_nocount Counter bypass.
5:0 mc_ckout0_dt[5:0] Counter delay.
Reg 08 ADDR: 0x08
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default       1 0 0 0 0 0 1 0 0 0 0 0 1
Access       R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
12 mc_ckout0_en Counter enable.
11:6 mc_ckout0_ht[5:0] Counter high time.
5:0 mc_ckout0_lt[5:0] Counter low time.
Reg 05 ADDR: 0x05
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0               0    
Access R/W R/W R/W R/W R/W R/W               R/W    
15:10 mc_in_dly_set[5:0] Counter delay setting. Control how much delay is inserted in the path.
9:4 mc_in_dly_mx_dvdd[5:0]
3 mc_direct_path_cntrl Reserved.
2 mc_in_dly_en Compensation delay enable.
Reg 00 ADDR: 0x00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default                         0   0  
Access                         R/W   R/W  
3 mc_inv_clkfbin Enable inversion on the CLKFBIN input. This is the same as setting the attribute IS_CLKFBIN_INVERTED to 1.
1 mc_inv_clkin Enable inversion on the CLKIN1 input. This is the same as setting the attribute IS_CLKIN1_INVERTED to 1.