PLL Primitives - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2025-05-29
Revision
1.11 English

The UltraScale device PLL primitives, PLLE3_BASE and PLLE3_ADV, are shown in the following figure. UltraScale+ devices have the same primitives with an E4 instead of an E3. In this user guide, PLLE4_ADV is the same as the PLLE3_ADV, and PLLE4_BASE is the same as PLLE3_BASE.

Figure 1. PLLE3 or PLLE4 Primitives

The Spartan UltraScale+ devices have PLLE4_BASE, PLLE4_ADV, PLLE4XP_BASE, and PLLE4XP_ADV primitives. The PLLE4XP is only present in Spartan UltraScale+ device CMTXPs that are adjacent to XP5IO banks.

Figure 2. PLLE4XP Primitives
Note: Apart from the ports in the PLLE4, RST_DMC, CLKOUTPHY_DMCEN, and LOCKED_DMC have been added which are used by the LPDDRMC. CLKOUTPHY_N has been removed from Spartan UltraScale+ devices with XP5IO.