The following table lists the attributes for the PLLE#_BASE and PLLE#_ADV primitives.
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| CLKOUT[0:1]_DIVIDE | Integer | 1 to 128 | 1 | Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number, in combination with the CLKFBOUT_MULT values, determines the output frequency. |
| CLKOUT[0:1]_ DUTY_CYCLE | Real | 0.01 to 0.99 | 0.50 | Specifies the duty cycle of the associated CLKOUT clock output in percentages (i.e., 0.50 generates a 50% duty cycle). |
| CLKFBOUT_MULT | Boolean | 1 to 19 | 5 | This CLKFBOUT_MULT range applies to UltraScale devices. Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency. |
| CLKFBOUT_MULT | Integer | 2 to 21 | 5 | This CLKFBOUT_MULT range applies to UltraScale+ devices. Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency. |
| DIVCLK_DIVIDE | Integer | 1 to 15 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. |
| REF_JITTER | Real | 0.000 to 0.999 | 0.010 | Allows specification of the expected jitter on the reference clock to better optimize PLL performance. A bandwidth setting of OPTIMIZED attempts to choose the best parameter for input clocking when unknown. If known, the value provided should be specified in terms of the unit interval (UI) (the maximum peak-to-peak value) of the expected jitter on the input clock. |
| CLKIN_PERIOD | Real | 0.938 to 14.286 | 0.000 | Specifies the input period in ns to the PLL CLKIN input. Resolution is down to the ps. This information is mandatory and must be supplied. |
| STARTUP_WAIT | String | FALSE, TRUE | FALSE | Wait during the configuration start-up cycle for the PLL to lock. |
| CLKOUT[0:1]_PHASE | Real | –360.000 to 360.000 | 0.000 | Allows specification of the output phase relationship of the associated CLKOUT clock output in number of degrees offset (i.e., 90 indicates a 90° offset or ¼ cycle phase offset while 180 indicates a 180° offset or ½ cycle phase offset). Valid phase shifts are in 360÷ CLKOUT[0:1]_DIVIDE degree increments. |
| CLKFBOUT_PHASE | Real | –360.000 to 360.000 | Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL. Valid phase shifts are in 360÷CLKFBOUT_MULT degree increments. | |
| COMPENSATION | String |
AUTO 1 , PHY_ALIGN, BUF_IN, INTERNAL |
AUTO |
Clock input compensation. Must be set to AUTO. Defines how the PLL feedback is configured. INTERNAL: Indicates that the PLL is using its own internal feedback path so no delay is being compensated. BUF_IN: Indicates that the clock network delay within the same XIPHY bank is compensated. Both CLKIN and CLKFB must be the same frequency at the PFD (FIN /D = FVCO /M). The feedback must be limited to within the same XIPHY and cannot be routed to adjacent banks or outside the device. PHY_ALIGN (for UltraScale+ devices only): allows fine- grained adjustments of the PLL output phase for the alignment of the XIPHY and internal logic flip-flops using the same source clock. Primarily for memory controller use. |
| CLKOUTPHY_MODE | String |
VCO_2X, VCO, VCO_HALF |
VCO_2X | Determines the clock output frequency based on the VCO frequency for the BITSLICE_CONTROL block. |
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Spartan UltraScale+ devices with XP5IO have additional attributes for the PLLE4XP_BASE and PLLE4P_ADV primitives. These are listed in the following table.
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| VCO_RANGE | String | Low, High | High | Determines the VCO frequency based on CLKIN_PERIOD (MHz) / DIVCLK_DIVIDE x CLKFBOUT_MULT. |