MMCM Registers

Reg 4F													ADDR: `0x4F`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0			0	0			0	0			0
Access	R/W			R/W	R/W			R/W	R/W			R/W
15	mc_res(3)					Loop filter resistor setting.
12	mc_res(2)
11	mc_res(1)
8	mc_res(0)
7	mc_lfhf(1)					Loop filter high frequency capacitor setting.
4	mc_lfhf(0)					Loop filter high frequency capacitor setting.

Reg 4E													ADDR: `0x4E`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0			0	0			0
Access	R/W			R/W	R/W			R/W
15	mc_cp(3)					Charge pump settings.
12	mc_cp(2)
11	mc_cp(1)
8	mc_cp(0)

Registers 0x4F and 0x4E define the values for the loop filters. Pick the appropriate values for these filters from the MMCM and PLL Dynamic Reconfiguration Application Note (XAPP888).

Reg 27													ADDR: `0x27`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0			0	0			1	0			0	0			0
Access	R/W			R/W	R/W			R/W	R/W			R/W	R/W			R/W
15	mc_interp_en(7)					Interpolator selection. Default value is `00010000` .
12	mc_interp_en(6)
11	mc_interp_en(5)
8	mc_interp_en(4)
7	mc_interp_en(3)
4	mc_interp_en(2)
3	mc_interp_en(1)
0	mc_interp_en(0)
If any of the output counters is using fine phase shift then mc_interp_en[3:0] must be set to `1111` otherwise mc_interp_en[3:0] must be set to `0000` . mc_interp_en(4) is always set to 1. If any of the output counters is using a phase of VCO other than 0 or 180, uses fractional division for a counter, or uses spread-spectrum mode then mc_interp_en[7:5] must be set to 111 otherwise mc_interp_en[7:5] must be set to 000.

Reg 1A													ADDR: `0x1A`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default		0	0	0	1	1	1	1	1	1	1	0	1	0	0	1
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
14:10	mc_lock_ref_dly[4:0]					Window setting for the lock circuit of the reference clock.
9:0	mc_lock_sat_high[9:0]					Maximum value of the lock counter. Default value is `d1001` .

Reg 19													ADDR: `0x19`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default		0	0	0	1	1	0	0	0	0	0	0	0	0	0	1
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
14:10	mc_lock_fb_dly[4:0]					Window setting for the lock circuit of the feedback clock.
9:0	mc_lock_sat_high[9:0]					Counter setting the number of clock cycles the MMCM needs to have CLKREF and CLKFB misaligned within a certain window before deasserting the LOCKED output. Default value is 1 .

Reg 18													ADDR: `0x18`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default							1	1	1	1	1	0	1	0	0	0
Access							R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
9:0	mc_lock_cnt[9:0]					Counter setting the number of clock cycles the MMCM needs to have CLKREF and CLKFB aligned within a certain window before the LOCKED output is asserted. Default value is `1000`.

Refer to MMCM and PLL Dynamic Reconfiguration Application Note (XAPP888) to determine the values for registers 0x1A, 0x19, and 0x18.

Reg 16													ADDR: `0x16`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default			0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
13	mc_divck_edge					High to low clock edge transition control.
12	mc_divck_nocount					Bypass counter.
11:6	mc_divck_ht[5:0]					Counter high time.
5:0	mc_divck_lt[5:0]					Counter low time.

Reg 15													ADDR: `0x15`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default		0	0	1	0	0			0	1	0	0	0	0	0	1
Access		R/W	R/W	R/W	R/W	R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
14:12	mc_ckfbout_frac[2:0]					Fractional phase.
11	mc_ckfbout_frac_en					Enable fractional counter.
10	mc_ckfbout_frac_wf_r					Fractional mode. Rising edge wait.
7	mc_ckfbout_edge					High to low clock edge transition control.
6	mc_ckfbout_nocount					Bypass counter.
5:0	mc_ckfbout_frac[5:0]					Counter delay.

Reg 14													ADDR: `0x14`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckfbout_pm_r[2:0]					VCO phase selection mux and rising edge control.
12	mc_ckfbout_en					Counter enable
11:6	mc_ckfbout_ht[5:0]					Counter high time
5:0	mc_ckfbout_lt[5:0]					Counter low time

Reg 13													ADDR: `0x13`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	0		0			0	1	0	0	0	0	0	0
Access	R/W	R/W	R/W	R/W		R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckfbout_pm_f[2:0]					VCO phase selection mux and falling edge control.
12	mc_ckfbout_frac_wf_f					Fractional mode. Falling edge wait.
10	mc_ckout6_cddc_en					Clock divide dynamic change enable (DRP only)
7	mc_ckout6_edge					High to low clock edge control
6	mc_ckout6_nocount					Counter bypass
5:0	mc_ckout6_dt[5:0]					Counter delay

Registers 0x15, 0x14, and bits [15:12] of 0x13 control the fractional feedback (M counter) shown in MMCMs.

Reg 12													ADDR: `0x12`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout6_pm[2:0]					VCO phase selection multiplexer
12	mc_ckout6_en					Counter enable
11:6	mc_ckout6_ht[5:0]					Counter high time
5:0	mc_ckout6_lt[5:0]					Counter low time

Bits [10:0] of register 0x13 and register 0x12 control the CLKOUT6 counter.

Reg 11													ADDR: `0x11`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default						0			0	1	0	0	0	0	0	0
Access						R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
10	mc_ckout4_cddc_en					Clock divide dynamic change control enable (DRP only).
7	mc_ckout4_edge					High to low clock edge control.
6	mc_ckout4_nocount					Counter bypass.
5:0	mc_ckout4_dt[5:0]					Counter delay.

Reg 10													ADDR: `0x10`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout4_pm[2:0]					VCO phase selection multiplexer.
12	mc_ckout4_en					Counter enable.
11:6	mc_ckout4_ht[5:0]					Counter high time.
5:0	mc_ckout4_lt[5:0]					Counter low time.

Registers 0x11 and 0x10 control the output counter for CLKOUT4.

Reg 0F													ADDR: `0x0F`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default						0			0	1	0	0	0	0	0	0
Access						R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
10	mc_ckout3_cddc_en					Clock divide dynamic change control enable (DRP only).
7	mc_ckout3_edge					High to low clock edge control.
6	mc_ckout3_nocount					Counter bypass.
5:0	mc_ckout3_dt[5:0]					Counter delay.

Reg 0E													ADDR: `0x0E`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout3_pm[2:0]					VCO phase selection multiplexer.
12	mc_ckout3_en					Counter enable.
11:6	mc_ckout3_ht[5:0]					Counter high time.
5:0	mc_ckout3_lt[5:0]					Counter low time.

Registers 0x0F and 0x0E control the output counter for CLKOUT3.

Reg 0D													ADDR: `0x0D`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default						0			0	1	0	0	0	0	0	0
Access						R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
10	mc_ckout2_cddc_en					Clock divide dynamic change control enable (DRP only).
7	mc_ckout2_edge					High to low clock edge control.
6	mc_ckout2_nocount					Counter bypass.
5:0	mc_ckout2_dt[5:0]					Counter delay.

Reg 0C													ADDR: `0x0C`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout2_pm[2:0]					VCO phase selection multiplexer.
12	mc_ckout2_en					Counter enable.
11:6	mc_ckout2_ht[5:0]					Counter high time.
5:0	mc_ckout2_lt[5:0]					Counter low time.

Registers 0x0D and 0x0C control the output counter for CLKOUT2.

Reg 0B													ADDR: `0x0B`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default						0			0	1	0	0	0	0	0	0
Access						R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
10	mc_ckout1_cddc_en					Clock divide dynamic change control enable (DRP only).
7	mc_ckout1_edge					High to low clock edge control.
6	mc_ckout1_nocount					Counter bypass.
5:0	mc_ckout1_dt[5:0]					Counter delay.

Reg 0A													ADDR: `0x0A`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout1_pm[2:0]					VCO phase selection multiplexer.
12	mc_ckout1_en					Counter enable.
11:6	mc_ckout1_ht[5:0]					Counter high time.
5:0	mc_ckout1_lt[5:0]					Counter low time.

Registers 0x0B and 0x0A control the output counter for CLKOUT1.

Reg 09													ADDR: `0x09`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	0		0			0	1	0	0	0	0	0	0
Access	R/W	R/W	R/W	R/W		R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15	mc_ckout0_cddc_en					Clock divide dynamic change control enable (DRP only).
14:12	mc_ckout0_frac[2:0]					Fractional phase.
11	mc_ckout0_frac_en					Enable fractional phase counter.
10	mc_ckout0_frac_wf_r					Falling edge wait.
7	mc_ckout0_edge					High to low clock edge control.
6	mc_ckout0_nocount					Counter bypass.
5:0	mc_ckout0_dt[5:0]					Counter delay.

Reg 08													ADDR: `0x08`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout0_pm_r[2:0]					Rising edge control.
12	mc_ckout0_en					Counter enable.
11:6	mc_ckout0_ht[5:0]					Counter high time.
5:0	mc_ckout0_lt[5:0]					Counter low time.

Reg 07													ADDR: `0x07`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	0		0			0	1	0	0	0	0	0	0
Access	R/W	R/W	R/W	R/W		R/W			R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout0_pm_f[2:0]					Falling edge control.
12	mc_ckout0_frac_wf_f					Rising edge wait.
10	mc_ckout0_cddc_en					Clock divide dynamic change control enable (DRP only).
7	mc_ckout5_edge					High to low clock edge control.
6	mc_ckout5_nocount					Counter bypass.
5:0	mc_ckout5_dt[5:0]					Counter delay.

The fractional output counter for CLKOUT0 is controlled by registers 0x09 , 0x08 , and bits [15:12] of register 0x07.

Reg 06													ADDR: `0x06`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
15:13	mc_ckout5_pm[2:0]					VCO phase selection multiplexer.
12	mc_ckout5_en					Counter enable.
11:6	mc_ckout5_ht[5:0]					Counter high time.
5:0	mc_ckout5_lt[5:0]					Counter low time.

Reg 05													ADDR: `0x05`
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Default	0	0	0	0	0	0
Access	R/W	R/W	R/W	R/W	R/W	R/W								R/W
15:10	mc_in_dly_set[5:0]					Counter delay setting. Control how much delay is inserted in the path.
9:4	mc_in_dly_mx_dvdd[5:0]
3	mc_direct_path_cntrl					Reserved.
2	mc_in_dly_en					Compensation delay enable.

Bits [10:0] of register 0x07 and register 0x06 control the CLKOUT5 counter.

The MMCM clock outputs are all defined by a configurable counter. The parameters defining the clock outputs CLKOUT6 to CLKOUT1 are explained in the following table. Refer to MMCM and PLL Dynamic Reconfiguration Application Note (XAPP888) for calculation instructions and methods.

Table 1. Clock Output Parameters
Type	Description
CDDC	Clock divide dynamic change. The possibility to change the DRP registers without the need for a MMCM reset. When this option is enabled it functions with the CDDCREQ and CDDCDONE handshake pins. For more information read MMCM Clock Divide Dynamic Change.
MX	Clock input multiplexer control.
EDGE	Clock edge identification. Identify the clock edge used for a high to low transition of the counter.
NOCOUNT	Counter bypass.
DT	Delay time. Counter delay or coarse phase shift setting.
PM	VCO phase selection. Used to select one of the eight possible VCO outputs.
EN	Counter enable.
HT	Counter high time. Set the delay the counter needs to output a high value.
LT	Counter low time. Set the delay the counter needs to output a low value.

Two of the counters, CLKFBOUT and CLKOUT0, are fractional counters. A fractional counter uses two non-fractional counters, an extra state, and adder logic. This is the reason a fractional counter has two enables (one for each counter to allow non-fractional use) and two VCO phase selection settings. For the adder and state logic, the VCO phase selection is extra split in rising and falling settings. Additional register configuration options defining the fractional counters are listed in the following table.

Table 2. Register Configuration Options
Type	Description
FRAC	Select a VCO phase to operate the fractional counter.
FRAC_EN	Enable the fractional counter.
FRAC_WF_R	Fractional counter wait for rising edge.
FRAC_WF_L	Fractional counter wait for falling edge.
PM_R	Select one of the eight VCO phased outputs as rising edge counter clock.
PM_L	Select one of the eight VCO phased outputs as falling edge counter clock.

Fractional counter mode is enabled when both mc_ckout_en and mc_ckout_frac_en are set. Both counters take different phases from the VCO outputs.

MMCM Registers - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)