Key Differences of Spartan UltraScale+ FPGAs from Other UltraScale+ FPGAs - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2025-05-29
Revision
1.11 English

In Spartan UltraScale+ devices, the CMTs adjacent to the integrated memory controller (LPDDRMC) and XP5IO have enhanced PLLs (PLLXP) with reserved ports for the LPDDRMC.