Example 2 - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)
Document ID
UG572
Release Date
2025-05-29
Revision
1.11 English

Assume a division by 2.125 is required, then:

  • Counter A would take phase 0 (0 degrees) of the VCO
  • Counter B would take as start phase 2 (45 degree offset)

Output starts High with rising edge on counter A and goes Low with second rising edge counter B. It goes High again with next rising edge of counter B, counter B switches to VCO phase 90 and the output goes Low again by the second rising edge of that phase and so on.

Figure 1. Fractional Counter Mode Example 2
Reg 04 ADDR: 0x04
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default                     1 0 0 1 1 1
Access                     R/W R/W R/W R/W R/W R/W
5:3 mc_ss_steps_init[2:0] Start the correct spread based on the SS_MODE attribute. Default value is 100.
2:0 mc_ss_steps[2:0] Control the spread of the spread-spectrum clocking based on the SS_MODE attribute. Default value is 111.

The settings for register 4 are controlled by the SS_MODE attribute of the MMCM. Refer to the Spread-Spectrum Clock Generation section for detailed information on spread-spectrum clocking set up and behavior.

  ss_steps_init ss_steps
DOWN_LOW 100 011
DOWN_HIGH 100 011
CENTER_LOW 100 111
CENTER_HIGH 100 111
Reg 00 ADDR: 0x00
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default                         0 0 0  
Access                         R/W R/W R/W  
3 mc_inv_clkfbin Enable inversion on the CLKFBIN input. This is the same as setting the attribute IS_CLKFBIN_INVERTED to 1.
2 mc_inv_clkin2 Enable inversion on the CLKIN2 input. This is the same as setting the attribute IS_CLKIN2_INVERTED to 1.
1 mc_inv_clkin1 Enable inversion on the CLKIN1 input. This is the same as setting the attribute IS_CLKIN1_INVERTED to 1.

Register 0 represents the bits that are also available as attributes of the MMCM primitive. For the functional explanation of these bits, refer to the MMCM Attributes section.