A BUFGMUX_CTRL with a clock enable BUFGCTRL configuration allows you to choose between the incoming clock inputs. If needed, the clock enable is used to disable the output. Figure 1 illustrates the BUFGCTRL usage design example and Figure 2 shows the timing diagram.
Figure 1. BUFGMUX_CTRL with a CE and BUFGCTRL
Figure 2. BUFGMUX_CTRL with a CE Timing Diagram
In the preceding figure:
- At time event 1, output O uses input I0.
- Before time event 2, S is asserted High.
- At time TBCCKO_O, after time event 2, output O uses input I1. This occurs after a High-to-Low transition of I0 followed by a High-to-Low transition of I1 is completed.
- At time TBCCCK_CE, before time event 3, CE is asserted Low. To avoid any output clock glitches, the clock output is switched Low and kept at Low until after a High-to-Low transition of I1 is completed.