The Watchdog timer has two modes (configuration monitor and user logic monitor), which are mutually exclusive of each other. In the more common configuration monitor mode, when the Watchdog Timer times out, the configuration logic loads the fallback bitstream. For situations where configuration does not begin, or begins properly but does not complete, such as for an invalid or a partially corrupted configuration source, the Watchdog timer allows the device to automatically re-attempt configuration after a reasonable delay. The Fallback MultiBoot section provides more details.
In configuration monitor mode, the TIMER register is set
in the BIT file by the bitstream generator. This timer value is then used for both the
configuration of the bitstream, which sets the value, as well as any subsequent loads
triggered by an IPROG command. The TIMER register needs to be set in
all BIT files.
The TIMER register counts down from the start to the
bitstream and is disabled by the end of the start-up sequence. If the count reaches 0, a
fallback is triggered. The start-up sequence can be delayed by the MMCM wait or DCI
match settings; these delays need to be taken into account. The TIMER register runs at
the CCLK frequency.
The Watchdog Timer can be enabled in the bitstream or through any configuration port by writing to the TIMER register. The Watchdog Timer is disabled during and after fallback reconfiguration. A successful IPROG reconfiguration initiated by a successful fallback reconfiguration is necessary to re-enable the Watchdog Timer.
In user logic monitor mode, the Watchdog Timer uses a
dedicated internal clock, CFGMCLK, which has a nominal frequency of 50
MHz. The clock is pre-divided by 256, so that the Watchdog Timer clock period is about
5,120 ns. Given the watchdog counter is 30 bits wide, the maximum possible watchdog
value is about 5,500 seconds. The time value can be set using the bitstream options.