The Watchdog timer is automatically disabled for fallback bitstreams. The name of each bit position in the Watchdog timer register (TIMER) is given in the following table and described in the subsequent table.
| Description | TIMER_USR_MON | TIMER_CFG_MON | TIMER_VALUE | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Bit Index | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | Bit Index | Description |
|---|---|---|
| TIMER_USR_MON | 31 |
Watchdog is enabled during user mode:
The watchdog clock in user mode is the CFGMCLK divided by 256. At a nominal CFGMCLK of 50 MHz and a tolerance of 15%, the watchdog clock would be 166–225 kHz. |
| TIMER_CFG_MON | 30 |
Watchdog is enabled during configuration:
The configuration watchdog clock is CCLK, as it is defined for configuration. When using EMCCLK, the Watchdog Timer runs off of the CCLK initially and then switches over to EMCCLK after the bitstream image header is read. |
| TIMER_VALUE | [29:0] | Watchdog time-out value. The default value is zero. |