Using Boundary-Scan Configuration in UltraScale FPGAs - Using Boundary-Scan Configuration in UltraScale FPGAs - UG570

One of the most common boundary-scan vendor-specific instructions is the Configure instruction. UltraScale architecture-based FPGAs support configuration through the standard boundary-scan (JTAG) port. If the device is configured via JTAG, the configure instructions occur independent from the selection on the mode pins. However, an explicit JTAG configuration mode setting is available when the devices are to be exclusively configured through the JTAG port. The JTAG mode pin setting restricts master ICAP access to slave SLRs, and therefore is not recommended for devices based on SSI technology. See the following figure for the pin connections for the JTAG configuration interface.

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.
3. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIO pins after power-up and during configuration. For BSDL compliance, PUDC_B should be tied to GND. See Configuration Pin Definitions for PUDC_B signal details.

AMD has USB proprietary programming cables and boundary-scan programming tools for prototyping purposes. These are not intended for production environments but can be highly useful for verifying FPGA implementations and JTAG chain integrity.

When trying to access other devices in the JTAG chain, it is important to know the size of the Instruction register length to ensure that the correct device receives the appropriate signals. This information can be found in the BSDL file for the device.

The FPGA boundary-scan operations are independent of mode selection. The boundary-scan mode overrides other mode selections. For this reason, boundary-scan instructions using the Boundary register (SAMPLE/PRELOAD and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a device is configured. After configuration, all instructions are available.

JSTART and JSHUTDOWN are instructions specific to the FPGA architecture and configuration flow. The TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.

The configuration flow for FPGA configuration with JTAG is shown in the following figure. A configured device can be reconfigured by toggling the TAP and entering a CFG_IN instruction after pulsing the PROGRAM_B pin or issuing the shutdown sequence. The JTAG state machine must be in the Shift-DR state during configuration with the CFG_IN instruction.