USR_ACCESSE2 - USR_ACCESSE2 - UG570

The USR_ACCESSE2 design element enables access to the 32-bit AXSS register within the configuration logic. This enables FPGA logic to access static data that can be set from the bitstream. The primitive and functionality for the UltraScale architecture-based FPGAs are identical to that for the 7 series.

The USR_ACCESSE2 register AXSS can be used to provide a single 32-bit constant value to the FPGA logic. The register contents can be defined during bitstream generation, avoiding the need to re-compile the design as would be required if distributed RAM was used to hold the constant. A constant can be used to track the version of the design, or any other information you require. This is an alternative to the JTAG USERCODE instruction, which reads a 32-bit value defined by the write_bitstream option BITSTREAM.Config.UserID. USR_ACCESSE2 has the advantage of being directly accessible by the FPGA logic, and can store an automatically generated timestamp.

The contents of the USR_ACCESSE2 register AXSS can be defined with the write_bitstream option BITSTREAM.Config.USR_ACCESS, which can be set to NONE (default all zeroes), any 8-character hex value, or TIMESTAMP.

TIMESTAMP inserts the current timestamp into the AXSS register in this format:

ddddd_MMMM_yyyyyy_hhhhh_mmmmmm_ssssss
(bit 31) ……………………………………………………… (bit 0)

Where:

ddddd = 5 bits to represent days 1-31 in a month
MMMM = 4 bits to represent months 1-12 in a year
yyyyyy = 6 bits to represent years 0-63 (2000 to 2063)
hhhhh = 5 bits to represent hours 0-23 in a day
mmmmmm = 6 bits to represent minutes 0-59 in an hour
ssssss = 6 bits to represent seconds 0-59 in a minute

For more details on USR_ACCESSE2, see Bitstream Identification with USR_ACCESS using the Vivado Design Suite (XAPP1232).