Timing Considerations for Flash Connections - Timing Considerations for Flash Connections - UG570

STARTUPE3 represents combinatorial connections, and does not contain any registers. Registers must be placed outside STARTUPE3. The USRCCLKO input to STARTUPE3 does not synchronize logic inside the block; it is a direct combinatorial connection to the CCLK pin after configuration. The USRCCLKO input would typically come from a global clock resource in the FPGA to synchronize the post-configuration interface to the flash. When using parallel NOR flash (BPI configuration), CCLK control is needed only if the flash supports synchronous transfers.

The STARTUPE3 does not support input or output delay constraints. As a result care should be taken to consider the performance requirements. The performance calculations are similar to those provided for calculating configuration frequency (see Figure 1 for SPI mode and Figure 1 through Figure 1 for BPI mode), but with the additional delays to and through the STARTUPE3 block. The delays between the STARTUPE3 ports and the device pins are noted in the data sheets Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) and Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893). Because timing constraints are not supported for STARTUPE3, constrain the routing connected to the STARTUPE3 ports.

The flash clock Low to output valid time (T_SPITCO for SPI mode) must take into account the CCLK delay through the STARTUPE3, T_USRCCLKO. For parallel NOR flash where transfers are done synchronously, T_CHQV is needed to add T_USRCCLKO.

Similarly, the FPGA data setup time (T_SPIDCC for SPI mode) on D[03:00] is delayed by the setup time from the pins to the STARTUPE3 DI ports (T_DI) plus the routing delays from the STARTUPE3 DI port outputs to the slice flip-flops used. For the three types of asynchronous transfers for parallel NOR flash used in BPI configuration, the output delays for address (T_BPICCO) need to be added to the input delay constraints and any flash delays (for example, T_APA, T_ACC). The output delay for address can be obtained by timing analysis.

Higher-order data pins D[xx:04] are routed directly to general-purpose I/O pins, so the delays can be constrained using standard input and output timing constraints. When setting input delays for serial NOR flash used in SPI mode, the clock polarity of the FPGA design must be taken into account. Data from the serial NOR flash device is launched off the falling edge of the clock.