The FPGA TAP contains four mandatory
dedicated pins as specified by the protocol and as used in the typical JTAG architecture
(see the following table). Three input pins and one output pin control the IEEE Std 1149.1
boundary-scan TAP controller. Optional control pins, such as Test Reset
(TRST) and enable pins, might be found on devices from other
manufacturers. It is important to be aware of these optional signals when interfacing AMD devices with parts from different vendors because these
optional pins might need to be driven.
| Pin | Direction | Pre-Configuration Internal Pull Resistor | Description |
|---|---|---|---|
| TDI | In | Pull-up |
Test Data In. This pin is the serial input to all JTAG instruction and data registers. The state of the TAP controller and the current instruction determine the register that is fed by the TDI pin for a specific operation. TDI has an internal resistive pull-up to provide a logic High to the system if the pin is not driven. TDI is applied to the JTAG registers on the rising edge of TCK. |
| TDO | Out | Pull-up |
Test Data Out. This pin is the serial output for all JTAG instruction and data registers. The state of the TAP controller and the current instruction determine the register (instruction or data) that feeds TDO for a specific operation. TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device. TDO is an active driver output. TDO has an internal resistive pull-up to provide a logic High if the pin is not active. |
| TMS | In | Pull-up |
Test Mode Select. This pin determines the sequence of states through the TAP controller, which change on the rising edge of TCK. TMS has an internal resistive pull-up to provide a logic High if the pin is not driven. |
| TCK | In | Pull-up |
Test Clock. This pin is the JTAG Test Clock. TCK sequences the TAP controller and the JTAG registers. TCK has an internal resistive pull-up to provide a logic High if the pin is not driven. |
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