The FPGA TAP contains four mandatory dedicated pins as specified by the protocol given in Table 1 and illustrated in the following table, a typical JTAG architecture.
The following figure shows a 16-state finite
state machine. The four TAP pins control how data is scanned into the various
registers. The state of the TMS pin at the rising edge of
TCK determines the sequence of state transitions. There are two main
sequences, one for shifting data into the data register and the other for shifting an
instruction into the Instruction register.
A transition between the states only occurs on the
rising edge of TCK, and each state has a different name. The two vertical
columns with seven states each represent the Instruction Path and the Data Path. The data
registers operate in the states whose names end with “DR,” and the Instruction register
operates in the states whose names end in “IR.” The states are otherwise identical.
The operation of each state is described as follows.
Test-Logic-Reset
All test logic is disabled in this
controller state, enabling the normal operation of the IC. The TAP controller state machine
is designed so that regardless of the initial state of the controller, the Test-Logic-Reset
state can be entered by holding TMS High and pulsing TCK
five times. Consequently, the Test Reset (TRST) pin is optional.
Run-Test-Idle
In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it is executed when the controller enters this state. The test logic in the IC is idle otherwise.
Select-DR-Scan
This controller state controls whether to enter the Data Path or the Select-IR-Scan state.
Select-IR-Scan
This controller state controls whether or not to enter the Instruction Path. The controller can return to the Test-Logic-Reset state otherwise.
Capture-IR
In this controller state, the shift
register bank in the Instruction Register parallel-loads a pattern of fixed values on the
rising edge of TCK. The last two significant bits must always be 01 .
Shift-IR
In this controller state, the Instruction
register gets connected between TDI and TDO, and the
captured pattern gets shifted on each rising edge of TCK. The instruction
available on the TDI pin is also shifted in to the Instruction
register.
Exit1-IR
This controller state controls whether to enter the Pause-IR state or Update-IR state.
Pause-IR
This state allows the shifting of the Instruction register to be temporarily halted.
Exit2-DR
This controller state controls whether to enter either the Shift-DR state or Update-DR state.
Update-IR
In this controller state, the instruction
in the Instruction register is latched to the latch bank of the Instruction register on
every falling edge of TCK. This instruction becomes the current instruction
after it is latched.
Capture-DR
In this controller state, the data is
parallel-loaded into the data registers selected by the current instruction on the rising
edge of TCK.
Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.
UltraScale
FPGAs support the mandatory IEEE Std 1149.1 commands as well as several AMD vendor-specific commands. The EXTEST,
SAMPLE/PRELOAD, BYPASS, IDCODE, and
USERCODE instructions are all included. The TAP also supports internal
user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the
device. INTEST is not supported. The HIGHZ_IO command is similar to the
standard HIGHZ command but only disables the user I/O pins.
For details on the standard boundary-scan
instructions EXTEST and BYPASS, refer to IEEE Std
1149.1.