Synchronous Read - Synchronous Read - UG570

For the fastest parallel NOR flash configuration time, use the master BPI Configuration mode synchronous x16 read option with the EMCCLK. There are several system factors that must be considered when you determine the maximum configuration clock rate for synchronous reads in your application. These following parameters should be considered:

• Flash clock to out (T_CHQV)
• FPGA data setup time (T_BPIDCC)
• External master configuration clock frequency (EMCCLK Rate) or FPGA nominal master CCLK frequency (configuration Rate)
• External master configuration clock frequency tolerance (EMCCLK Tolerance) or FPGA master CCLK frequency tolerance (FMCCKTOL)

The following example uses the EMCCLK. The parallel NOR flash clock-to-out and the FPGA setup data sheet specifications are used to determine the maximum EMCCLK frequency. Board trace delay is also another factor that should be considered. An estimation for the maximum BPI Fast Configuration EMCCLK can be calculated with the following equation and must be less than the supported EMCCLK frequency (FEMCCK) specified in the FPGA data sheet.

For an application targeting a supported parallel NOR flash with a clock-to-out specification of T_CHQV = 5.5 ns and an FPGA data setup of T_BPIDCC = 3.5 ns, under the best case with EMCCLK clock tolerance and board delay negligible would be approximately 111 MHz which is less than the specified EMCCLK frequency (FEMCCK).