The following figure shows the sequence to
initiate the BPI configuration synchronous read. The master BPI mode sequence occurs
automatically after power-up when the bitstream has been generated with the synchronous read
option and the mode pins are set to M[2:0] = 010 .
First, the FPGA reads the bitstream asynchronously
to determine the targeted read option. The read always starts at the default internal
CCLK rate. After the INIT_B signal is released and the
control signals FCS_B, FOE, and ADV_B are asserted with a
valid address A[28:00] then data is captured from the parallel NOR flash on
the data bus D[15:0]. The FPGA reads the bitstream header to determine the
flash read option selected for reading the configuration data. When a synchronous command is
read in the bitstream header, the FPGA configuration controller initiates an asynchronous
write to the Read Configuration Register (RCR) of the connected parallel NOR flash.
Next, the FPGA writes the flash RCR synchronous
and latency bits to enable a flash synchronous read. To perform the asynchronous write
operation, the FPGA asserts the FCS_B and FWE_B while the
INIT_B and FOE_B are deasserted. The FPGA issues the Flash
Configuration register write sequence of two write cycles. The first cycle has the Read
Configuration Register (RCR) data on A[16:01] and command 0x60 on the data bus. The second cycle has the RCR data on
A[16:01] and the command 0x03 on the data
bus. The RCR values are different for the different flash families and are determined by the
bitstream options, described in File Generation.
Lastly, the FPGA switches from the asynchronous
read to synchronous read protocol and reinitiates the bitstream read. This sequence is
implemented by the FPGA asserting the FCS_B and the FOE_B
signals and having ADV_B asserted for one cycle with a valid address. The
configuration data is then burst from the flash and read back by the FPGA. Once the header
information is read, the configuration clock source can change to the user selection.