For BPI, slave SelectMAP, and master SelectMAP modes, the bus
width must be first detected (refer to Bus Width Auto Detection). The bus width
detection pattern is ignored by slave serial, master serial, SPI, and JTAG modes. Then, a
special 32-bit synchronization word (0xAA995566) must be sent to the
configuration logic. The synchronization word alerts the device to upcoming configuration data
and aligns the configuration data with the internal configuration logic. Any data on the
configuration input pins prior to synchronization is ignored, except the Bus Width Auto Detection sequence.
Synchronization (see the previous figure) is transparent to most users because all configuration bitstreams (BIT files) generated by the tools include both the bus width detection pattern and the synchronization word. The following table shows signals relating to synchronization.
| Signal Name | Type | Access | Description |
|---|---|---|---|
| DALIGN | Status | Only available through the SelectMAP interface during an ABORT sequence. | Indicates whether the device is synchronized. |
| IWIDTH | Status | Internal signal. Accessed only through the FPGA status register. 1 The status register CFG_BUS_WIDTH_DETECTION bits indicate the detected bus width. |
Indicates the detected bus width:
If ICAPE3 is enabled, this signal reflects the ICAPE3 width after configuration is done. |
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