Status Register for Fallback and IPROG Reconfiguration - Status Register for Fallback and IPROG Reconfiguration - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

UltraScale architecture-based FPGAs contain a BOOTSTS register that stores configuration history. BOOTSTS operates similar to a two-entry FIFO. The most recent configuration status is stored in Status_0, and the current value for Status_0 is shifted into Status_1. The Valid_0 bit indicates if the rest of Status_0 is valid or not. See Boot History Status Register (10110).

The following tables show the BOOTSTS values in some common situations.

Table 1. Status after First Bitstream Configuration without Error
  Reserved WRAP_ERROR CRC_ERROR ID_ERROR WTO_ERROR IPROG FALLBACK VALID
Status_1 0 0 0 0 0 0 0 0
Status_0 0 0 0 0 0 0 0 1
Table 2. First Configuration Followed by IPROG
  Reserved WRAP_ERROR CRC_ERROR ID_ERROR WTO_ERROR IPROG FALLBACK VALID
Status_1 0 0 0 0 0 0 0 1
Status_0 0 0 0 0 0 1 0 1
Table 3. IPROG Embedded in First Bitstream, Second Bitstream CRC Error, Fallback Successfully
  Reserved WRAP_ERROR CRC_ERROR ID_ERROR WTO_ERROR IPROG FALLBACK VALID
Status_1 0 0 1 0 0 1 0 1
Status_0 0 0 0 0 0 1 1 1

Notes for the previous table:

  1. Status_1 shows IPROG was attempted, and a CRC_ERROR was detected for that bitstream.
  2. Status_0 shows a fallback bitstream was loaded successfully. The IPROG bit was also set in this case, because the fallback bitstream contains an IPROG command. Although the IPROG command is ignored during fallback, the status still records this occurrence.

For an example design, see MultiBoot and Fallback with SPI Flash in UltraScale FPGAs Application Note (XAPP1257).