The starting point for internal debugging should always be the status
register, which requires access to the JTAG port. FPGA status register data can be read in the
AMD Vivado™
device programmer through JTAG. For example, if the
DONE and INIT_B signals are Low, this register captures
the specific error conditions that can help identify the type of failure. In addition, the
status register allows you to verify the mode pin settings M[2:0] and the bus
width detect. Details on status register use are provided in Status Register (00111).