Status Register (00111) - Status Register (00111) - UG570

UltraScale Architecture Configuration User Guide (UG570)
Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The status register (STAT) indicates the value of numerous global signals. The register can be read through the SelectMAP or JTAG interfaces. The following table gives the name of each bit position in the STAT register; a detailed explanation of each bit position is given in the subsequent table.

Table 1. Status Register
Description Reserved CFGBVS_PIN BAD_PACKET_ERROR PUDC_B_PIN SECURITY_AUTH_ERROR CFG_BUS_WIDTH_DETECTION Reserved SECURITY_STATUS CFG_STARTUP_STATE_MACHINE_PHASE SYSTEM_MONITOR_OVER_TEMP SECURITY_VIOLATION IDCODE_ERROR DONE_PIN DONE_INTERNAL_SIGNAL_STATUS INIT_B_PIN INIT_B_INTERNAL_SIGNAL_STATUS MODE_PIN_M[2:0] GHIGH_B_STATUS GWE_STATUS GTS_CFG_B_STATUS END_OF_STARTUP_(EOS)_STATUS DCI_MATCH_STATUS MMCM_PLL_LOCKED DECRYPTOR_ENABLED CRC_ERROR
Bit Index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Table 2. Status Register Description
Name Bit Index Description
CFGBVS_PIN 30 Value on CFGBVS Pin. Not applicable for UltraScale+ FPGAs.
BAD_PACKET_ERROR 29 Unexpected packet detected.
PUDC_B_PIN 28 Value on PUDC_B Pin.
SECURITY_AUTH_ERROR 27 Security authentication error or a security violation occurred.

CFG_BUS_WIDTH_

DETECTION

 [26:25]

Bus width auto detection result. This is the width of the internal configuration bus (not necessarily the same as the external configuration data width). For BPI and SelectMAP modes, value is set to 01 (x8) after mode pins are sampled and before bus width detection. If ICAPE3 is enabled, this field reflects the ICAPE3 bus width after configuration is done. RSA authentication sets the bus width to x32.

00 = x1

01 = x8

10 = x16

11 = x32
SECURITY_STATUS [23:21]

Security Status

• [21]: BBRAM key, AES expanded Key, Key Update register and AES eFuse in eFUSE cache are zero when set to 1.

• [22]: GCM or RSA authentication failure when set to 1.

• [23]: AES expanded key and Key Update register are all zero when set to 1.

CFG_STARTUP_STATE_

MACHINE_PHASE

 [20:18]

Start-up state machine (0 to 7):

Phase 0 = 000

Phase 1 = 001

Phase 2 = 011

Phase 3 = 010

Phase 4 = 110

Phase 5 = 111

Phase 6 = 101

Phase 7 = 100

SYSTEM_MONITOR_OVER_TEMP 17 System Monitor over-temperature.
SECURITY_VIOLATION 16

Security violation:

0: No SECURITY_VIOLATION

1: SECURITY_VIOLATION
IDCODE_ERROR 15

Attempt to write to FDRI without successful DEVICE_ID check:

0: No IDCODE_ERROR

1: IDCODE_ERROR
DONE_PIN 14 Value on DONE_PIN pin.
DONE_INTERNAL_SIGNAL_STATUS 13

Value of internal DONE_INTERNAL_SIGNAL_STATUS signal:

0: Signal not released (pin is actively held Low)

1: Signal released (can be held Low externally)
INIT_B_PIN 12 Value on INIT_B_PIN pin
INIT_B_INTERNAL_SIGNAL_STATUS 11

Internal signal indicating initialization has completed:

0: Initialization has not finished

1: Initialization finished
MODE_PIN_M[2:0] [10:8] Status of the mode pins (M[2:0]).
GHIGH_B_STATUS 7

Status of GHIGH_B_STATUS:

0: GHIGH_B_STATUS asserted

1: GHIGH_B_STATUS deasserted
GWE_STATUS 6

Status of GWE:

0: Flip-flops and block RAM are write disabled

1: Flip-flops and block RAM are write enabled
GTS_CFG_B_STATUS 5

Status of GTS_CFG_B:

0: All I/Os are placed in High-Z state

1: All I/Os behave as configured
END_OF_STARTUP_(EOS)_STATUS 4

End of start-up signal from start-up block:

0: Start-up sequence has not finished

1: Start-up sequence has finished
DCI_MATCH_STATUS 3

This bit is a logical AND function of all the MATCH signals (one per bank). If no DCI I/Os are in a particular bank, the bank MATCH signal = 1.

0: DCI not matched

1: DCI is matched
MMCM_PLL_LOCKED 2

This bit is a logical AND function of all MMCM/PLL LOCKED signals. Unused MMCM/PLL LOCKED signals = 1.

0: MMCMs/PLLs are not locked

1: MMCMs/PLLs are locked
DECRYPTOR_ENABLED 1

0: Decryptor security not set

1: Decryptor security set
CRC_ERROR 0

0: No CRC error

1: CRC error