After the configuration frames are loaded, the bitstream instructs the device to enter the start-up sequence (see the previous figure). The start-up sequence is controlled by an 8-phase (phases 0-7) sequential state machine. The start-up sequencer performs the tasks outlined in the following table.
| Phase | Event |
|---|---|
| 1-6 | Wait for MMCMs to lock (optional) |
| 1-6 | Wait for DCI to match (optional) |
| 1-6 | Assert global write enable (GWE), allowing RAMs and flip-flops to change state |
| 1-6 | Negate global 3-state (GTS), activating I/O |
| 1-6 | Release DONE pin |
| 7 | Assert end of start-up (EOS) |
The specific order of start-up events (except for
EOS assertion) is user-programmable through bitstream options controlled by
the BITSTREAM.STARTUP properties (refer to the
Vivado Design Suite User Guide:
Programming and Debugging (UG908)). The following table shows the general sequence of events, although the
specific phase for each of these start-up events is user-programmable (EOS is
always asserted in the last phase). By default, start-up events occur as shown in the
following table.
| Phase | Event |
|---|---|
| 4 | Release DONE pin |
| 5 | Negate Global 3-State (GTS), activating I/O |
| 6 | Assert GWE, allowing RAMs and flip-flops to change state |
| 7 | Assert End Of Start-up (EOS) |
The start-up sequence can be forced to wait for
the MMCMs to lock or for DCI to match with the appropriate bitstream options. These options
are typically set to prevent DONE, GTS, and
GWE from being asserted (preventing device operation) before the MMCMs have
locked and/or DCI has matched.
DCIUpdateMode is set to AsRequired, there will be an
indeterministic delay after start-up until those pins are calibrated. If
DCIUpdateMode is set to Quiet, the pins would never have
their DCI values set. To avoid these issues, the DCIRESET primitive should be included, and
the design should pulse the RST input of DCIRESET and then wait for the LOCKED signal to be
asserted prior to using any user input or outputs on the multi-function pins with DCI
standards. For more details on DCI, see the
UltraScale
Architecture SelectIO Resources User Guide (UG571).The DONE signal is released by
the start-up sequencer on the cycle indicated by the user options, but the start-up sequencer
does not proceed until the DONE pin actually sees a logic High. The
DONE pin is an open-drain bidirectional signal. By releasing the
DONE pin, the device stops driving a logic Low, and the pin is pulled up by
a default internal pull-up resistor. There is no setup or hold requirement for the DONE
register. The following table shows signals relating to the start-up sequencer. The following
figure shows the waveforms relating to the start-up sequencer.
| Signal Name | Type | Access 1 | Description |
|---|---|---|---|
| DONE | Bidirectional 2 | DONE pin or FPGA status register | Indicates configuration is complete. Can be held Low externally to synchronize start-up with other FPGAs. |
| Release_DONE | Status | FPGA status register | Indicates whether the device has stopped driving the DONE pin Low. If the pin is held Low externally, Release_DONE can differ from the actual value on the DONE pin. |
| GWE 3 | Global write enable (GWE). When asserted High, GWE enables the RAM, CLB flip-flops, and other synchronous elements on the FPGA. | ||
| GTS | Global 3-state (GTS). When asserted High, GTS disables all the I/O drivers except for the configuration pins. | ||
| EOS | End of start-up (EOS). EOS indicates the absolute end of the configuration and start-up process. | ||
| DCI_MATCH | DCI_MATCH indicates when all the digitally controlled impedance (DCI) controllers have matched their internal resistor to the external reference resistor. | ||
|
MMCM_PLL_ LOCKED |
Asserted by default, or when MMCMs and PLLs have locked if the STARTUP_WAIT option is used. | ||
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