Slave Serial Configuration - Slave Serial Configuration - UG570

Slave serial configuration is typically used for devices in a serial daisy chain or when configuring a single device from an external microprocessor or CPLD (see the following figure). Design considerations are similar to master serial configuration except for the direction of CCLK. CCLK must be driven from an external clock source, which also provides data (see Clocking Serial Configuration Data).

Notes relevant to the previous figure:

1. The DONE pin is by default an open-drain output. See Configuration Pin Definitions for DONE signal details.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required. See Configuration Pin Definitions for INIT_B signal details.
3. CCLK signal integrity is critical.
4. See the respective data sheet Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) or Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) for the V_CCINT, V_CCAUX, and V_{CCO_0} supply voltages.
5. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIOpins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.