Slave Modes - Slave Modes - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID
UG570
Release Date
2025-03-04
Revision
1.20.1 English

The externally controlled loading FPGA configuration modes, generically called slave modes, are also available with either a serial or parallel datapath. In slave mode, an external processor, microcontroller, DSP processor, or tester downloads the configuration image into the FPGA, as shown in the following figure. The advantage of the slave configuration modes is that the FPGA bitstream can reside almost anywhere in the overall system. The bitstream can reside in flash along with the host processor's code, on a hard disk, or somewhere over a network connection.

Figure 1. Slave Configuration Modes

The slave serial mode is an uncomplicated interface that consists of a clock and serial data input. The slave SelectMAP mode is a x8-, x16-, or x32-bit-wide processor peripheral interface, including a chip-select input and a read/write control input.