Single Device SelectMAP Configuration - Single Device SelectMAP Configuration - UG570

For custom applications where a microprocessor or CPLD is used to configure a single FPGA, either master SelectMAP mode (use CCLK from the FPGA) or slave SelectMAP mode can be used (see the following figure). Slave SelectMAP mode is preferred. See Using a Microprocessor to Configure 7 Series FPGAs via Slave Serial or Slave SelectMAP Mode (XAPP583) for information on configuring AMD FPGAs using a microprocessor.

Notes relevant to the previous figure:

1. Refer toUsing a Microprocessor to Configure 7 Series FPGAs via Slave Serial or Slave SelectMAP Mode (XAPP583), for a discussion of one possible implementation.
2. The processor or CPLD I/O needs to support a voltage that is compatible with the connected FPGA pins.
3. The DONE pin is an open-drain output. See Configuration Pin Definitions for DONE signal details.
4. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required. See Configuration Pin Definitions for INIT_B signal details.
5. The CSI_B and RDWR_B signals can be tied to GND if only one FPGA is going to be configured and readback is not needed.
6. CCLK signal integrity is critical.
7. Data bus width can be x8, x16, or x32 for slave SelectMAP configuration.
8. The FPGA PUDC_B pin is tied to GND to enable internal pull-ups or it can be tied to V_{CCO_0} to 3-state the SelectIOpins after power-up and during configuration. See Configuration Pin Definitions for PUDC_B signal details.