Single Device Configuration - Single Device Configuration

Single Device Configuration - Single Device Configuration - UG570

UltraScale Architecture Configuration User Guide (UG570)

Document ID

UG570

Release Date

2025-03-04

Revision

1.20.1 English

The following table describes the TAP controller commands required to configure an UltraScale FPGA. Refer to Figure 2 for TAP controller states. These TAP controller commands are issued automatically if configuring the part with the AMD Vivado™ device programmer. For encrypted bitstreams using an obfuscated key with the JTAG interface, do not pause bitstream loading by temporary excursion from the JTAG Shift-DR state to the JTAG Pause-DR state. Instead, stay within the JTAG Shift-DR state and stop the JTAG TCK clock to pause bitstream loading. See answer record 73656 for details.

Table 1. Single Device Configuration Sequence
TAP Controller Step and Description		Set and Hold		No. of Clocks
TAP Controller Step and Description		TDI	TMS	TCK
1	On power-up, place a logic `1` on the TMS, and clock the TCK five times. This ensures starting in the Test-Logic-Reset (TLR) state.	`X`	`1`	5
2	Move to the Run-Test/Idle (RTI) state.	`X`	`0`	1
3	Move to the SELECT-IR state.	`X`	`1`	2
4	Move to the SHIFT-IR state.	`X`	`0`	2
5	Start loading the JPROGRAM instruction, LSB first:	`01011` ¹	`0`	5
6	Load the MSB of the JPROGRAM instruction when exiting SHIFT-IR, as defined in the IEEE standard.	`0`	`1`	1
7	Move to the UPDATE-IR state.	X	1	1
8	Move to the SELECT-IR state.	X	1	2
9	Move to the SHIFT-IR state.	X	0	2
10	Start loading the CFG_IN instruction, LSB first:	`00101`	`0`	5
11	Load the MSB of the CFG_IN instruction when exiting SHIFT-IR.	`0`	`1`	1
12	Move to the UPDATE-IR state.	X	`1`	1
13	Move to the RTI state and wait for t_POR delay.	X	`0`	20,000²
14	Move to the SELECT-DR state.	X	`1`	1
15	Move to the SHIFT-DR state.	X	`0`	2
16	Shift in the FPGA bitstream. Bit n (MSB) is the first bit in the bitstream.^{3 4}	Bit 1 ... bit n	`0`	(bits in bitstream) -1
17	Shift in the last bit of the bitstream. Bit 0 (LSB) shifts on the transition to EXIT1-DR.	Bit 0	`1`	1
18	Move to the UPDATE-DR state.	X	`1`	1
19	Move to the RTI state.	X	`0`	1
20	Move to the SELECT-IR state.	X	`1`	2
21	Move to the SHIFT-IR state.	X	`0`	2
22	Start loading the JSTART instruction (optional). The JSTART instruction initializes the startup sequence.	`01100`	`0`	5
23	Load the MSB of the JSTART instruction when exiting SHIFT_IR.	`0`	`1`	1
24	Move to the UPDATE-IR state.	X	`1`	1
25	Move to the RTI state and clock the startup sequence by applying a minimum of 2,000 clock cycles to the TCK.	X	`0`	2,000
26	Move to the TLR state. The device is now functional.	X	`1`	3
Instruction register is larger for devices based on SSI technology (see Table 2). See the BSDL files for device-specific information. Assumes a t_POR wait time of 20 ms is necessary until INIT_B is High and CFG_IN can be sent. In this example, the TCK cycle value is based on a TCK frequency of 1 MHz. In the Configuration register, data is shifted in from the right (TDI) to the left (TDO), MSB first. Shifts into the configuration register are different from shifts into the other registers in that they are MSB first. For 3D ICs based on Stacked Silicon Interconnect (SSI) technology, the JTAG TAP must stay in the SHIFT-DR state until the entire bitstream is shifted into the device in step 16, with the only exception being bit 0 which is shifted in step 17.