Serial NOR flash densities over 128 Mb require more than the
traditional 24-bit addressing that was standard before the introduction of 256 Mb and larger
flashes. Flash vendors use various methods to support 32-bit addressing that might enable the
24-bit read commands to operate as a 32-bit read command. For example, a nonvolatile bit might
be set in the flash that causes the flash to expect four address bytes after a
0Bh command. These methods should not be enabled for the flash devices used
to configure UltraScale FPGAs.
The solution supported by the UltraScale FPGAs
requires the flash to boot up in a 24-bit addressing mode for the 0Bh,
3Bh, and 6Bh commands and 32-bit addressing for the
0Ch, 3Ch, and 6Ch commands. The Vivado tool Edit Device Properties
dialog box provides the option to enable 32-bit addressing. To generate a bitstream for flash
densities over 128 Mb the property BITSTREAM.CONFIG.SPI_32BIT_ADDR should be set to Yes. See
Vivado Design Suite User Guide:
Programming and Debugging (UG908) for details. Valid flash devices must support the
instructions in Table 1 (SPI Instructions and
Required Opcodes) to interface with the UltraScale FPGAs.