Multiple FPGAs can be configured from a
single configuration source by arranging the devices in a serial daisy chain. In a serial
daisy chain, devices receive their configuration data through their DIN pin, passing
configuration data along to downstream devices through their DOUT pin. Data
on DOUT is clocked out on the falling edge of CCLK. Data is
captured on DIN of the downstream device on the rising edge of
CCLK. The device closest to the configuration data source is considered the
most upstream device, while the device furthest from the configuration data source is
considered the most downstream device.
In a serial daisy chain, the configuration clock is typically provided by the most upstream device in SPI mode. All other devices are set for slave serial mode. The following figure illustrates this configuration.
Notes relevant to the previous figure:
- The
DONEpin is by default an open-drain output. See Configuration Pin Definitions forDONEsignal details. - The
INIT_Bpin is a bidirectional, open-drain pin. An external pull-up resistor is required. - See Figure 1 for a more detailed view of the master SPI connections.
- Fallback MultiBoot is not supported in this configuration.
The first device in a serial daisy chain is the last to be configured. CRC checks only include the data for the current device, not for any others in the chain. (See CRC Check (Step 7).)
After the last device in the chain finishes
configuration and passes its CRC check, it enters the start-up sequence. At the release
DONE pin phase in the start-up sequence, the device places its
DONE pin in a high-Z state while the next to the last device in the chain
is configured. After all devices release their DONE pins, the common
DONE signal is pulled High externally. On the next rising
CCLK edge, all devices move out of the release DONE pin
phase and complete their start-up sequences.
It is important that all DONE
pins in a slave serial daisy chain be connected.