CCLK is an output in master SelectMAP mode and an input in slave SelectMAP mode. Slave SelectMAP mode is recommended; master SelectMAP mode is not supported in the AMD Artix™ UltraScale+™ , AMD Kintex™ UltraScale+™ , and AMD Virtex™ UltraScale+™ FPGAs. Master SelectMAP is supported in the AMD Kintex™ UltraScale™ and Virtex UltraScale FPGAs for legacy applications. AMD Platform Flash PROMs do not support the UltraScale architecture-based FPGAs. For parallel modes, BPI configuration is recommended.
Readback and the read direction of the data bus are applicable only to slave SelectMAP mode. The bus width of SelectMAP is automatically detected. One or more devices can be configured through the SelectMAP bus.
There are multiple methods of configuring an FPGA in SelectMAP mode:
- Single-device slave SelectMAP
- Typical setup includes a processor providing data and clock. Alternatively, another programmable logic device, such as a CPLD, can be used as a configuration manager that configures the FPGA through the FPGA slave SelectMAP interface.
- Multiple-device daisy-chain SelectMAP bus
- Multiple FPGAs are configured in series with different images from a flash memory or processor.
- Multiple-device ganged SelectMAP
- Multiple FPGAs are configured in parallel with the same image from a flash memory or processor.
The basic master SelectMAP and slave SelectMAP configuration methods are described in this chapter.
The SelectMAP configuration interface pins shown in the following figure are defined in Configuration Pin Definitions.
