3D ICs do not support the ABORT sequence. In monolithic
devices an ABORT is an interruption in the SelectMAP configuration or readback sequence
occurring when the state of RDWR_B changes while CSI_B is
asserted as sampled by CCLK. During a configuration ABORT, internal status is
driven onto the D[04:07] pins over the next four CCLK
cycles. The other D pins are always High. After the ABORT sequence finishes,
the user can resynchronize the configuration logic and resume configuration. For applications
that must deassert RDWR_B between bytes, see the Controlled
CCLK method shown in the previous figure.